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Das Einbetten von Halbleiterbauelementen stellt einen innovativen Ansatz für die Aufbau- und Verbindungstechnik (AVT) leistungselektronischer Systeme dar. Im Rahmen von zahlreichen Forschungsvorhaben wurde gezeigt, dass im Vergleich zu einer konventionellen AVT geringere parasitäre Induktivitäten und Widerstände [1, 2]und damit geringere Leitungs- und Schaltverluste ermöglicht werden. Auch kann der thermische Widerstand durch den Einsatz von Dickkupfersubstraten und wärmeleitfähigen organischen Isolatoren erheblich reduziert werden [2, 3, 4]. Dadurch lässt sich auf Systemebene eine höher Leistungsdichte erreichen [5], ohne dass dadurch die Lastwechselfestigkeit leidet [6, 3].
Dennoch findet die Technologie bis heute nur im Low-Power Bereich oder zum Chip-Scale Packaging von einzelnen Leistungsschaltern kommerziellen Einsatz.
Dieser Vortrag diskutiert mögliche Hemmnisse und Grenzen der Technologie.
Embedding power semiconductor devices into printed circuit boards (PCB) provides several benefits compared to conventional packaging technologies. Integrating the semiconductor dies into the circuit board reduces the converter size. This results in short current loops, enabling low interconnection resistances and parasitic inductances. Both contribute to a higher system-level efficiency, as conduction and switching losses are reduced. Moreover, the use of thick Cu substrates allows efficient heat removal, due to a low thermal resistance. Therefore, PCB embedding has received a lot of attention in the power electronics community for more than a decade. This article aims to provide a comprehensive review of the scientific literature on the topic ranging from basic fabrication technology over module or system-level demonstrators for electrical and thermal testing to reliability studies. Performance indicators, such as the commutation loop inductance Lσ, the chip area independent thermal resistance Rth × Achip, allow a comparison of different approaches and benchmarking with conventional power modules. Several publications report stray inductances below 1 nH and chip area independent thermal resistances in the range of 20…30 mm²K/W.
This paper presents a novel integration concept for mid-voltage power semiconductor modules. The concept is based on a dielectric liquid that is used for both, cooling and insulation. The semiconductor chips are attached to Cu inlays in a PCB substrate. Dual side cooling is achieved jet by impingement on the bottom side and immersion in the dielectric liquid on the top side. A first laboratory demonstrator was designed and build-up with 2.0 kV rated SiC MOSFETs in a 140×100 mm² module package. Shell immersion cooling fluid S5 LV was applied as coolant. Test results indicate a junction to fluid thermal resistance of 0.54 K/W at a flow rate of 5 l/min and with pressure drop of 12 kPa. The results obtained are on the same level compared with a state- -the-art automotive power of modules with a pin-fin array integrated in the baseplate and water-glycol as coolant.
Embedding represents a game-changing packaging strategy for wide-bandgap semiconductors, slashing parasitic impedances to enable faster, cleaner switching, lower losses, and higher frequencies. Yet questions about reliability, scalability, and heat management persist. Here, we use multiphysics finite-element simulations to explore an embedded half-bridge of two 1.2 kV SiC MOSFETs across a range of commercial insulated substrates - alumina, Si 3 N4, AlN, and IMS with varying layer thicknesses. A Pareto-based thermomechanical optimization pinpoints aluminum nitride as the best configuration, delivering 0.27K/W thermal resistance, 0.2 % plastic strain, and 1.9 % creep strain during sintering. Creep concentrates in the silver sinter layer, matching experimental observations, underscoring the need to address time-dependent deformation in reliability assessments. A major improvement is achieved by redesigning the top copper interconnect from a solid block to a pillar like geometry, which reduces creep strain in the sintered layer by four times. We also identify a critical sintering cool-down rate above which creep vanishes and only plastic strain remains providing a new lever for process control. Finally, we demonstrate scalability by paralleling four optimized prepackages into a power module with just 3 nH of stray inductance, ready for high-frequency, high-efficiency conversion.
This paper presents a novel approach to embed power semiconductor devices into a printed circuit board. Here, IGBTs and diodes with reinforced top side chip contact are used in an IGBT half bridge with 25 A / 1200 V rating. Thermal simulations highlight the improved thermal impedance caused by the reinforced top contact and the benefits of the insulated copper substrate compared to a commercial DBC-based reference module.
The fabrication process is discussed in detail and preliminary test results are presented. The results of the thermal characterization support the theoretical
considerations.
PCB embedding is an attractive packaging technology for highly integrated future power systems. Electrical and thermal benefits and limitations are well understood, but only few publications focus on reliability. Here we are addressing high-humidity high temperature reverse bias (H3TRB) tests, which are performed to gain deeper understanding of the limitations of this technology. Cu filament growth is observed on both, PCB embedded samples and silicone potted reference samples. These filaments may form a conductive path and lead to an increased leakage current in blocking mode. Electrochemical corrosion of the Cu-plated guard ring is identified as root cause.
Embedding power semiconductor devices in pre-packages may enable low-inductive power semiconductor module designs with superior thermal performance and reliability. However, it is crucial to understand mechanical stress formation due to the differences in thermal expansion of the materials used. This paper presents a systematic study of thermomechanical stresses in Si and SiC power semiconductor pre-packages based on PCB embedding or compression molding. The analysis is based on thermomechanical FEM simulations and complemented by passive thermal cycling of different test carrier designs. Patterning and CTE-matching of contacts are proven as strategies to minimize thermomechanical stress.
This work investigates a packaging solution for high voltage semiconductors (20 kV), allowing for a dramatic reduction in size and complexity of power electronics modules. The standard packaging structures typically introduce a competition between electrical insulation (which requires thick insulating layers) and thermal performance (where thin, high thermal conductivity layers are preferred). Here, we introduce a concept which addresses this competition and is based on direct cooling using dielectric liquid. Single-chip heatsinks are designed, optimized using computational fluid dynamics (CFD), built and tested.
This work investigates a packaging solution for high power density semiconductors (> 200 W/cm 2), allowing for a dramatic reduction in size and complexity of power electronics modules. The multiple layers in standard packaging structures degrade the cooling efficiency due as they lengthen the path between dies and heatsinks. Here, we reduce the layer count by merging the ceramic substrate and the heat exchanger in a single part. CFD simulations and experimental validation are performed on a single-chip cooling packaging, and demonstrate a 10-20 % reduction in thermal resistance over more traditional cooling solutions.