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Das Einbetten von Halbleiterbauelementen stellt einen innovativen Ansatz für die Aufbau- und Verbindungstechnik (AVT) leistungselektronischer Systeme dar. Im Rahmen von zahlreichen Forschungsvorhaben wurde gezeigt, dass im Vergleich zu einer konventionellen AVT geringere parasitäre Induktivitäten und Widerstände [1, 2]und damit geringere Leitungs- und Schaltverluste ermöglicht werden. Auch kann der thermische Widerstand durch den Einsatz von Dickkupfersubstraten und wärmeleitfähigen organischen Isolatoren erheblich reduziert werden [2, 3, 4]. Dadurch lässt sich auf Systemebene eine höher Leistungsdichte erreichen [5], ohne dass dadurch die Lastwechselfestigkeit leidet [6, 3].
Dennoch findet die Technologie bis heute nur im Low-Power Bereich oder zum Chip-Scale Packaging von einzelnen Leistungsschaltern kommerziellen Einsatz.
Dieser Vortrag diskutiert mögliche Hemmnisse und Grenzen der Technologie.
PCB embedding is an attractive packaging technology for highly integrated future power systems. Electrical and thermal benefits and limitations are well understood, but only few publications focus on reliability. Here we are addressing high-humidity high temperature reverse bias (H3TRB) tests, which are performed to gain deeper understanding of the limitations of this technology. Cu filament growth is observed on both, PCB embedded samples and silicone potted reference samples. These filaments may form a conductive path and lead to an increased leakage current in blocking mode. Electrochemical corrosion of the Cu-plated guard ring is identified as root cause.
This paper presents a novel approach to embed power semiconductor devices into a printed circuit board. Here, IGBTs and diodes with reinforced top side chip contact are used in an IGBT half bridge with 25 A / 1200 V rating. Thermal simulations highlight the improved thermal impedance caused by the reinforced top contact and the benefits of the insulated copper substrate compared to a commercial DBC-based reference module.
The fabrication process is discussed in detail and preliminary test results are presented. The results of the thermal characterization support the theoretical
considerations.
This work investigates a packaging solution for high voltage semiconductors (20 kV), allowing for a dramatic reduction in size and complexity of power electronics modules. The standard packaging structures typically introduce a competition between electrical insulation (which requires thick insulating layers) and thermal performance (where thin, high thermal conductivity layers are preferred). Here, we introduce a concept which addresses this competition and is based on direct cooling using dielectric liquid. Single-chip heatsinks are designed, optimized using computational fluid dynamics (CFD), built and tested.
This work investigates a packaging solution for high power density semiconductors (> 200 W/cm 2), allowing for a dramatic reduction in size and complexity of power electronics modules. The multiple layers in standard packaging structures degrade the cooling efficiency due as they lengthen the path between dies and heatsinks. Here, we reduce the layer count by merging the ceramic substrate and the heat exchanger in a single part. CFD simulations and experimental validation are performed on a single-chip cooling packaging, and demonstrate a 10-20 % reduction in thermal resistance over more traditional cooling solutions.
Embedding power semiconductor devices in pre-packages may enable low-inductive power semiconductor module designs with superior thermal performance and reliability. However, it is crucial to understand mechanical stress formation due to the differences in thermal expansion of the materials used. This paper presents a systematic study of thermomechanical stresses in Si and SiC power semiconductor pre-packages based on PCB embedding or compression molding. The analysis is based on thermomechanical FEM simulations and complemented by passive thermal cycling of different test carrier designs. Patterning and CTE-matching of contacts are proven as strategies to minimize thermomechanical stress.
This paper presents design, fabrication, and analysis of a PCB embedded half-bridge. Here, a pre-package that contains a 100 V / 100 A MOSFET half bridge is fabricated and embedded into a converter level power PCB, allowing for two routing layers on top of the semiconductors. This enables to minimize the commutation loop inductance by placing a decoupling capacitor directly on top of the switches. Experimentally a parasitic inductance of 1.4 nH is deducted from the ringing frequency in switching experiments. The second design goal is an optimized thermal
performance. Both, simulation with ANSYS Icepak and experiments indicate a value of 1.77 K/W. Based on the results, a 12 V / 48 V bidirectional converter was implemented and operated with a maximum power of 620 W.
Thermal impedance evaluation of optimized PCB-based GaN HEMT Single-ChipPrepackage using VGS Method
(2022)
This study evaluates the measurement of the thermal resistance and impedance of GaN HEMTs packages with gatesource voltage (VGS) for junction temperature measurement. First, calibration measurement of VGS vs temperature is performed in an oven. Large deviations from chip to chip require that each device is calibrated separately. Zth is measured for an experimental single-chip prepackage (SCP), developed in our lab, and a commercial reference package (GaNpx). The measured junction to ambient thermal resistance of the SCP is 35% lower compared to the reference. This is caused by a copper heat spreader integrated in the package. The thermal resistance of multiple packages attached on one PCB is also performed. This measurement indicates a maximum difference of 35%. This difference remained the same in several experiments with two thermal interface materials and pressure levels.
PCB embedding in combination with direct-bonded copper (DBC) substrates is an attractive approach for packaging of power semiconductors facilitating low-inductive designs while relying on a proven insulating material. However, the CTE mismatch of these materials could cause reliability issues. This study presents an initial reliability screening using simple IGBT prepackages with alumina-based DBC as test vehicles. After -40/150 °C temperature cycles, fracture of the substrate and the chip is observed, resulting in an increased on-state resistance. Literature data suggest that the substrate failure is independent from the embedding. To gain a deeper understanding of the limitations of the technology, further research with optimized DBC substrates is required.
Leiterplattenembedding von Halbleiterbauelementen für die Leistungselektronik – vom Modul zum System
(2018)
Das Einbetten von Halbleiterbauelementen in Leiterplatten ist ein alternativer Ansatz zur Steigerung der Leistungsdichte und Funktionalität von leistungselektronischen Systemen. Diese Arbeit stellt ein neuartiges Verfahren vor, bei dem die Halbleiter nach der Leiterplattenfertigung in Kavitäten eingebettet werden. Die Betriebscharakteristik derartiger Leiterplattenmodule werden systematisch an Hand eines 1200V/50A Demonstrators untersucht. Ein Benchmark mit einem herkömmlichen, kommerziell verfügbaren Leistungsmodul mit identischen Halbleiterbauelementen verdeutlicht die Vorteile der Technologie: die parasitären Widerstände und Induktivitäten des Embedded-Moduls sind gegenüber der Referenz um 86% bzw. 65% verringert. Der thermische Widerstand fällt um 29% niedriger aus. Mit diesen Daten wurde eine theoretische Analyse auf Systemebene durchgeführt, wobei ein 23kW Antriebsumrichter als Beispielanwendung dient. Alleine durch das Leiterplattenembedding ist eine Steigerung der Ausgangsleistung um 14,5% möglich. Eingriffe in die Schaltungstechnik sind dazu nicht notwendig.
Leiterplattenembedding von Halbleiterbauelementen für die Leistungselektronik – vom Modul zum System
(2018)
Das Einbetten von Halbleiterbauelementen in Leiterplatten ist ein alternativer Ansatz zur Steigerung der Leistungsdichte und Funktionalität von leistungselektronischen Systemen. Diese Arbeit stellt ein neuartiges Verfahren vor, bei dem die Halbleiter nach der Leiterplattenfertigung in Kavitäten eingebettet werden. Die Betriebscharakteristik derartiger Leiterplattenmodule wird systematisch an Hand eines 1200 V / 50 A Demonstrators untersucht. Ein Benchmark mit einem herkömmlichen, kommerziell verfügbaren Leistungsmodul mit identischen Halbleiterbauelementen verdeutlicht die Vorteile der Technologie: die parasitären Widerstände und Induktivitäten des EmbeddedModuls sind gegenüber der Referenz um 86 % bzw. 65 % verringert. Der thermische Widerstand fällt um 29 % niedriger aus. Mit diesen Daten wurde eine theoretische Analyse auf Systemebene durchgeführt, wobei ein 23 kW Antriebsumrichter als Beispielanwendung dient. Alleine durch das Leiterplattenembedding ist eine Steigerung der Ausgangsleistung um 14,5 % möglich. Eingriffe in die Schaltungstechnik sind dazu
nicht notwendig.
This paper presents a novel fabrication concept for PCB embedded power semiconductors. Here, the semiconductors are attached to an insulated metal substrate, which is embedded in a second step into an almost-ready PCB. This approach avoids handling of bare dies during PCB production. To demonstrate the feasibility of the concept, a 1200 V / 50 A B6 bridge is designed and fabricated. The performance is evaluated and benchmarked. Compared to a conventional DBCbased power module, the conduction losses are reduced by 21% and the thermal resistance is reduced by 29%. Turn-off losses are 25% lower, while turn-on losses are about the same for both module types. A further optimization of the switching performance is possible, but requires a reduced DC-link inductance and an optimization of the gate resistance.
This paper presents a modular fabrication concept for printed circuit board embedded power semiconductors. The fabrication is done in a two step approach. First, the Single-Switch-Pre-Packages (SSPP) are built using standard embedding processes. Subsequently, full converters are fabricated by embedding of the SSPP as functional inlays into a PCB-power module. For optimal heat spreading, the semiconductor dies are silver sintered on a thick copper substrate. To exploit further the potential of the substrate, heat exchanger structures are chemically etched on it. Dielectric coolant serves as the cooling medium in this case. Laboratory demonstrators are built and characterization is performed as proof-of-concept. Thermal test indicates an junction to ambient thermal resistance of 0.43 K/W, compared to 0.8 K/W for reference module on a standard cold plate with water glycol. The hydraulic power and coolant temperature were identical for both cases.
PCB embedding is a novel and promising approach for packaging of power semiconductors. Due to the planar construction the technology enables lower conduction and switching losses, an increase switching frequency and ultimately yields a higher power density. Usually embedding is performed during lay-up of the PCB. Here, a novel concept for fabrication of PCB based power devices is proposed. The bare dies are sandwiched between two circuit boards using Ag sintering and simultaneous lamination of prepregs. The technology is discussed with reference to a 600V / 50A IGBT half bridge module. Using high-Tg isolator material in the PCB, a suitable process window is established and laboratory demonstrators are fabricated. An electrical characterization proves the feasibility of the concept.
Tests are carried out on two different series-connected switches made of six SiC MOSFETs capable of blocking 10 kV and 20 kV respectively. High voltage capacitors are connected to the drain terminals of the MOSFETs to emulate the common mode currents’ paths due to parasitic capacitances of the packaging. Due to high dV/dt, common mode currents become dangerous to the switch as they unsettle the voltage sharing during turn-off and unbalance switching losses. This could lead some of the MOSFETs to experience avalanche breakdown. A novel packaging approach that suppresses or balances the common mode currents is introduced.
This study investigated the thermal performance of a packaging solution designed to manage the electrical isolation and cooling of high voltage ( ) SiC power semiconductor > 3300 V devices. The proposed packaging merges the ceramic substrate and the heat exchanger into a single component, streamlining the overall design. Specifically, a novel heat exchanger is developed for a multi-chip module (20 kV), utilizing a combination of jet impingement and channel- flow cooling techniques. Computational fluid dynamics (CFD) simulations and experimental validation are conducted on a multi-chip module to assess the thermal resistance of this new cooling solution. The results demonstrate a
low thermal resistivity of 0.118 cm2K/W, indicating the potential for improved cooling performance in high voltage and power density semiconductor applications.
Embedding power semiconductor devices into printed circuit boards (PCB) provides several benefits compared to conventional packaging technologies. Integrating the semiconductor dies into the circuit board reduces the converter size. This results in short current loops, enabling low interconnection resistances and parasitic inductances. Both contribute to a higher system-level efficiency, as conduction and switching losses are reduced. Moreover, the use of thick Cu substrates allows efficient heat removal, due to a low thermal resistance. Therefore, PCB embedding has received a lot of attention in the power electronics community for more than a decade. This article aims to provide a comprehensive review of the scientific literature on the topic ranging from basic fabrication technology over module or system-level demonstrators for electrical and thermal testing to reliability studies. Performance indicators, such as the commutation loop inductance Lσ, the chip area independent thermal resistance Rth × Achip, allow a comparison of different approaches and benchmarking with conventional power modules. Several publications report stray inductances below 1 nH and chip area independent thermal resistances in the range of 20…30 mm²K/W.
The use of packaging technologies which allow thick leadframes and thus a high heat spread with metal substrates close to semiconductors, promise a better thermal performance of power modules, especially when using modern GaN or SiC power transistors with high power density. However, the degrees of freedom in the dimensioning of these metal substrates with regard to area, thickness, symmetry and chip positioning are large and optimization towards minimum thermal resistance results in unnecessarily large and unmanufacturable leadframes with high parasitic inductance, which hinders fast switching. In this paper the influence of geometric parameters of the leadframe on the thermal performance is investigated based on thermostatic 3D FEM simulations of a half-bridge with symmetrical losses. From this thermal analysis the dimensioning for a GaN half-bridge with high thermal requirements for a low inductance commutation cell is derived.
This paper proposes an asymmetric Single-Chip-Prepackage (SCP) with thick Cu substrate for the optimum electrical and thermal performance of the GaN-HEMT devices. Additionally, the package features a Ni-based integrated thermistor. Laboratory demonstrators have been fabricated using PCB embedding technology. A full electrical characterization of the packaged device indicates full functionality. The temperature coefficient of the integrated temperature sensor is 𝛼 = 0.00541 /𝐾. Thermal characterization of the SCP shows a junction to heatsink thermal resistance Rth,jh = 3.34 K/W, which is 36 % less than the commercial reference device. A silver sinter based assembly process for system integration of SCP is introduced in view of a planar thermal interface. In a 300 kHz 48 V to 24 V buck-converter operation with 60 Arms output current, a 98% efficiency is achieved.