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Embedding power semiconductor devices in pre-packages may enable low-inductive power semiconductor module designs with superior thermal performance and reliability. However, it is crucial to understand mechanical stress formation due to the differences in thermal expansion of the materials used. This paper presents a systematic study of thermomechanical stresses in Si and SiC power semiconductor pre-packages based on PCB embedding or compression molding. The analysis is based on thermomechanical FEM simulations and complemented by passive thermal cycling of different test carrier designs. Patterning and CTE-matching of contacts are proven as strategies to minimize thermomechanical stress.
PCB embedding in combination with direct-bonded copper (DBC) substrates is an attractive approach for packaging of power semiconductors facilitating low-inductive designs while relying on a proven insulating material. However, the CTE mismatch of these materials could cause reliability issues. This study presents an initial reliability screening using simple IGBT prepackages with alumina-based DBC as test vehicles. After -40/150 °C temperature cycles, fracture of the substrate and the chip is observed, resulting in an increased on-state resistance. Literature data suggest that the substrate failure is independent from the embedding. To gain a deeper understanding of the limitations of the technology, further research with optimized DBC substrates is required.
Wide bandgap semiconductors, SiC and GaN-based power devices represent key candidates in the development of more efficient devices due to their superior electrical and thermal properties compared to silicon. To achieve maximal performance from WBG semiconductors, new packaging technologies and thermo-electric designs must be developed to ensure efficient and fast switching of devices while minimizing losses. The paper aims to investigate the thermal and mechanical behavior of new prepackage embedding technologies by finite element simulation. The focus is on insulated substrates including direct bonded copper (DBC) with various dielectrics such as AlN, Al 2O 3, Si3N 4 and new insulated metal substrates (IMS) with emphasis on commercially available materials and thicknesses. This study proposes a thermo-mechanical pareto-optimization methodology able to identify the best substrate configuration. The sintered silver layer (in both sides of the chip), which is the most prone to failure due to delamination, has been modelled with a temperature-dependent bilinear hardening model to account for plasticity. Pareto-optimization accounts for the module thermal resistance and the plastic strain or Von Mises Stress in the sintered layer. Results demonstrate that the best candidate from the thermo-mechanical point of view is the DBC with AlN showing a thermal resistance of 0.34 K/W, accumulative plastic strain of 0.18 % and Von Mises stress of 274 MPa. Finally, the parasitic inductance of multiple pre-packages is evaluated to scale the power of the module. Proper design allows to achieve a stray inductance as small as 1.23 nH for two prepackages and 2.85 nH for four prepackages.