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Leiterplattenembedding von Halbleiterbauelementen für die Leistungselektronik – vom Modul zum System
(2018)
Das Einbetten von Halbleiterbauelementen in Leiterplatten ist ein alternativer Ansatz zur Steigerung der Leistungsdichte und Funktionalität von leistungselektronischen Systemen. Diese Arbeit stellt ein neuartiges Verfahren vor, bei dem die Halbleiter nach der Leiterplattenfertigung in Kavitäten eingebettet werden. Die Betriebscharakteristik derartiger Leiterplattenmodule werden systematisch an Hand eines 1200V/50A Demonstrators untersucht. Ein Benchmark mit einem herkömmlichen, kommerziell verfügbaren Leistungsmodul mit identischen Halbleiterbauelementen verdeutlicht die Vorteile der Technologie: die parasitären Widerstände und Induktivitäten des Embedded-Moduls sind gegenüber der Referenz um 86% bzw. 65% verringert. Der thermische Widerstand fällt um 29% niedriger aus. Mit diesen Daten wurde eine theoretische Analyse auf Systemebene durchgeführt, wobei ein 23kW Antriebsumrichter als Beispielanwendung dient. Alleine durch das Leiterplattenembedding ist eine Steigerung der Ausgangsleistung um 14,5% möglich. Eingriffe in die Schaltungstechnik sind dazu nicht notwendig.
Leiterplattenembedding von Halbleiterbauelementen für die Leistungselektronik – vom Modul zum System
(2018)
Das Einbetten von Halbleiterbauelementen in Leiterplatten ist ein alternativer Ansatz zur Steigerung der Leistungsdichte und Funktionalität von leistungselektronischen Systemen. Diese Arbeit stellt ein neuartiges Verfahren vor, bei dem die Halbleiter nach der Leiterplattenfertigung in Kavitäten eingebettet werden. Die Betriebscharakteristik derartiger Leiterplattenmodule wird systematisch an Hand eines 1200 V / 50 A Demonstrators untersucht. Ein Benchmark mit einem herkömmlichen, kommerziell verfügbaren Leistungsmodul mit identischen Halbleiterbauelementen verdeutlicht die Vorteile der Technologie: die parasitären Widerstände und Induktivitäten des EmbeddedModuls sind gegenüber der Referenz um 86 % bzw. 65 % verringert. Der thermische Widerstand fällt um 29 % niedriger aus. Mit diesen Daten wurde eine theoretische Analyse auf Systemebene durchgeführt, wobei ein 23 kW Antriebsumrichter als Beispielanwendung dient. Alleine durch das Leiterplattenembedding ist eine Steigerung der Ausgangsleistung um 14,5 % möglich. Eingriffe in die Schaltungstechnik sind dazu
nicht notwendig.
This paper presents a novel fabrication concept for PCB embedded power semiconductors. Here, the semiconductors are attached to an insulated metal substrate, which is embedded in a second step into an almost-ready PCB. This approach avoids handling of bare dies during PCB production. To demonstrate the feasibility of the concept, a 1200 V / 50 A B6 bridge is designed and fabricated. The performance is evaluated and benchmarked. Compared to a conventional DBCbased power module, the conduction losses are reduced by 21% and the thermal resistance is reduced by 29%. Turn-off losses are 25% lower, while turn-on losses are about the same for both module types. A further optimization of the switching performance is possible, but requires a reduced DC-link inductance and an optimization of the gate resistance.
This paper presents a modular fabrication concept for printed circuit board embedded power semiconductors. The fabrication is done in a two step approach. First, the Single-Switch-Pre-Packages (SSPP) are built using standard embedding processes. Subsequently, full converters are fabricated by embedding of the SSPP as functional inlays into a PCB-power module. For optimal heat spreading, the semiconductor dies are silver sintered on a thick copper substrate. To exploit further the potential of the substrate, heat exchanger structures are chemically etched on it. Dielectric coolant serves as the cooling medium in this case. Laboratory demonstrators are built and characterization is performed as proof-of-concept. Thermal test indicates an junction to ambient thermal resistance of 0.43 K/W, compared to 0.8 K/W for reference module on a standard cold plate with water glycol. The hydraulic power and coolant temperature were identical for both cases.
PCB embedding is a novel and promising approach for packaging of power semiconductors. Due to the planar construction the technology enables lower conduction and switching losses, an increase switching frequency and ultimately yields a higher power density. Usually embedding is performed during lay-up of the PCB. Here, a novel concept for fabrication of PCB based power devices is proposed. The bare dies are sandwiched between two circuit boards using Ag sintering and simultaneous lamination of prepregs. The technology is discussed with reference to a 600V / 50A IGBT half bridge module. Using high-Tg isolator material in the PCB, a suitable process window is established and laboratory demonstrators are fabricated. An electrical characterization proves the feasibility of the concept.
Tests are carried out on two different series-connected switches made of six SiC MOSFETs capable of blocking 10 kV and 20 kV respectively. High voltage capacitors are connected to the drain terminals of the MOSFETs to emulate the common mode currents’ paths due to parasitic capacitances of the packaging. Due to high dV/dt, common mode currents become dangerous to the switch as they unsettle the voltage sharing during turn-off and unbalance switching losses. This could lead some of the MOSFETs to experience avalanche breakdown. A novel packaging approach that suppresses or balances the common mode currents is introduced.
This study investigated the thermal performance of a packaging solution designed to manage the electrical isolation and cooling of high voltage ( ) SiC power semiconductor > 3300 V devices. The proposed packaging merges the ceramic substrate and the heat exchanger into a single component, streamlining the overall design. Specifically, a novel heat exchanger is developed for a multi-chip module (20 kV), utilizing a combination of jet impingement and channel- flow cooling techniques. Computational fluid dynamics (CFD) simulations and experimental validation are conducted on a multi-chip module to assess the thermal resistance of this new cooling solution. The results demonstrate a
low thermal resistivity of 0.118 cm2K/W, indicating the potential for improved cooling performance in high voltage and power density semiconductor applications.
Embedding power semiconductor devices into printed circuit boards (PCB) provides several benefits compared to conventional packaging technologies. Integrating the semiconductor dies into the circuit board reduces the converter size. This results in short current loops, enabling low interconnection resistances and parasitic inductances. Both contribute to a higher system-level efficiency, as conduction and switching losses are reduced. Moreover, the use of thick Cu substrates allows efficient heat removal, due to a low thermal resistance. Therefore, PCB embedding has received a lot of attention in the power electronics community for more than a decade. This article aims to provide a comprehensive review of the scientific literature on the topic ranging from basic fabrication technology over module or system-level demonstrators for electrical and thermal testing to reliability studies. Performance indicators, such as the commutation loop inductance Lσ, the chip area independent thermal resistance Rth × Achip, allow a comparison of different approaches and benchmarking with conventional power modules. Several publications report stray inductances below 1 nH and chip area independent thermal resistances in the range of 20…30 mm²K/W.
The use of packaging technologies which allow thick leadframes and thus a high heat spread with metal substrates close to semiconductors, promise a better thermal performance of power modules, especially when using modern GaN or SiC power transistors with high power density. However, the degrees of freedom in the dimensioning of these metal substrates with regard to area, thickness, symmetry and chip positioning are large and optimization towards minimum thermal resistance results in unnecessarily large and unmanufacturable leadframes with high parasitic inductance, which hinders fast switching. In this paper the influence of geometric parameters of the leadframe on the thermal performance is investigated based on thermostatic 3D FEM simulations of a half-bridge with symmetrical losses. From this thermal analysis the dimensioning for a GaN half-bridge with high thermal requirements for a low inductance commutation cell is derived.
This paper proposes an asymmetric Single-Chip-Prepackage (SCP) with thick Cu substrate for the optimum electrical and thermal performance of the GaN-HEMT devices. Additionally, the package features a Ni-based integrated thermistor. Laboratory demonstrators have been fabricated using PCB embedding technology. A full electrical characterization of the packaged device indicates full functionality. The temperature coefficient of the integrated temperature sensor is 𝛼 = 0.00541 /𝐾. Thermal characterization of the SCP shows a junction to heatsink thermal resistance Rth,jh = 3.34 K/W, which is 36 % less than the commercial reference device. A silver sinter based assembly process for system integration of SCP is introduced in view of a planar thermal interface. In a 300 kHz 48 V to 24 V buck-converter operation with 60 Arms output current, a 98% efficiency is achieved.