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Das Einbetten von Halbleiterbauelementen stellt einen innovativen Ansatz für die Aufbau- und Verbindungstechnik (AVT) leistungselektronischer Systeme dar. Im Rahmen von zahlreichen Forschungsvorhaben wurde gezeigt, dass im Vergleich zu einer konventionellen AVT geringere parasitäre Induktivitäten und Widerstände [1, 2]und damit geringere Leitungs- und Schaltverluste ermöglicht werden. Auch kann der thermische Widerstand durch den Einsatz von Dickkupfersubstraten und wärmeleitfähigen organischen Isolatoren erheblich reduziert werden [2, 3, 4]. Dadurch lässt sich auf Systemebene eine höher Leistungsdichte erreichen [5], ohne dass dadurch die Lastwechselfestigkeit leidet [6, 3].
Dennoch findet die Technologie bis heute nur im Low-Power Bereich oder zum Chip-Scale Packaging von einzelnen Leistungsschaltern kommerziellen Einsatz.
Dieser Vortrag diskutiert mögliche Hemmnisse und Grenzen der Technologie.
PCB embedding is an attractive packaging technology for highly integrated future power systems. Electrical and thermal benefits and limitations are well understood, but only few publications focus on reliability. Here we are addressing high-humidity high temperature reverse bias (H3TRB) tests, which are performed to gain deeper understanding of the limitations of this technology. Cu filament growth is observed on both, PCB embedded samples and silicone potted reference samples. These filaments may form a conductive path and lead to an increased leakage current in blocking mode. Electrochemical corrosion of the Cu-plated guard ring is identified as root cause.
The embedding of power electronics components into the PCB increases their thermal and electrical performance. Due to lower parasitic inductances and a lower thermal resistance, the overall power density of the system can be increased. However, there is a lack on studies about the reliability of PCB embedded power electronics, especially under humidity stress. This study uses test vehicles with functional diodes embedded into the PCB. The reliability of the test vehicles is studied under HV-H3TRB conditions. A critical leakage current is observed after 200h with a benzoxazine based prepreg and after 600h for an epoxy based prepreg. A rootcause analysis revealed lift-off of the polyimide layer and subsequent electrochemical corrosion as failure mechanism. The delamination is most likely triggered by the Au surface on the chips top metal pad. A second set of test samples was fabricated using an improved surface treatment before lamination. 75% of these samples passed the 1000h H3TRB test successfully.
Previously, a novel concept for PCB embedding of power semiconductors with reinforced top contacts has been published by our group. In this work, a thermomechanical study is performed to understand the fracture probability of the chip during fabrication. The ball-on-ring (BOR) and ball-on-edge (BOE) tests are employed to characterize the chip strength. A probabilistic model is used to evaluate the failure probability. The contribution of different fabrication steps to the overall failure probability is investigated. A parametric analysis is performed to analyze the impact of material choice and the thickness of the substrate and the interposer. A single-step sintered package with a 200 μm thick Cu interposer and an 800 μm thick Cu substrate with hard Cu leads to a 12% failure probability compared to 52% for an identical stack with a soft Cu substrate. The top surface failure probability for a 150 μm thick CIC interposer is 0.016% compared to 8.6% for a 100 μm Cu interposer., for an identical 800μm thick Cu substrate. A sinterlamination process, where the die-attach and curing of the prepreg material simultaneously take place, results in a 0.03% failure probability.