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This work investigates a packaging solution for high voltage semiconductors (20 kV), allowing for a dramatic reduction in size and complexity of power electronics modules. The standard packaging structures typically introduce a competition between electrical insulation (which requires thick insulating layers) and thermal performance (where thin, high thermal conductivity layers are preferred). Here, we introduce a concept which addresses this competition and is based on direct cooling using dielectric liquid. Single-chip heatsinks are designed, optimized using computational fluid dynamics (CFD), built and tested.
This study investigated the thermal performance of a packaging solution designed to manage the electrical isolation and cooling of high voltage ( ) SiC power semiconductor > 3300 V devices. The proposed packaging merges the ceramic substrate and the heat exchanger into a single component, streamlining the overall design. Specifically, a novel heat exchanger is developed for a multi-chip module (20 kV), utilizing a combination of jet impingement and channel- flow cooling techniques. Computational fluid dynamics (CFD) simulations and experimental validation are conducted on a multi-chip module to assess the thermal resistance of this new cooling solution. The results demonstrate a
low thermal resistivity of 0.118 cm2K/W, indicating the potential for improved cooling performance in high voltage and power density semiconductor applications.