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Institute
We present a numerical and experimental design study for reducing conducted common mode noise for frequencies below 10MHz generated in switching cells comprising sub-nH commutation loops. Compared to conventional methods of adding external gate resistors our approach does not degrade efficiency. A parallel plate loop design (characterized by a minimum loop inductance and small board area usage) is found suboptimal in terms of conducted EMI compared to a micro-strip line loop geometry. The net ground impedance rather than the net ground inductance is found to mainly contribute to the observed EMI noise.
Wide-bandgap semiconductors such as Silicon Carbide (SiC) or Gallium Nitride (GaN) enable fast switching and high switching frequencies of power electronics. However, this potential can not be exploited due to limitations caused by parasitic elements of packaging and interconnections. This paper shows a possibility to minimize parasitic elements of a half-bridge switching cell with 650 V GaN dies integrated into a printed circuit substrate. A sub-nH commutation loop of 0.5 nH inductance gives superior switching characteristics compared to circuits with packaged dies. Simulation and experimental results of an inverse double pulse test confirm our expectations. This study further reveals additional benefits of the proposed technology in terms of mechanical stability and thermal interfacing to heat sinks compared to circuits with packaged dies.
Power cycling and temperature endurance test of a GaN switching cell with substrate integrated chips
(2019)
We present a reliability study of a half-bridge switching cell with substrate integrated 650 V GaN HEMTs. Power Cycling Testing with a ΔTj of 100 K has revealed thermo-mechanically induced failures of contact vias after more than 220 kcycles. The via failure mode of contact opening is confirmed by reverse-bias pulsed IV-measurements to be primarily triggered by a ΔTj imposed thermal gradient and not by a high Tj. The chip electrical characteristics, however, remained unaffected during Power Cycling. Furthermore, a High Temperature Storage test at 125 °C for 5000 h has shown no changes in the electrical performance of substrate integrated GaN HEMTs.
This paper proposes an ultra-low inductance half-bridge switching cell with substrate integrated 650V GaN bare dies. A vertical parallel-plate waveguide structure with 100 μm layer thickness results in a commutation loop inductance of 0.5 nH resulting in a negligible drain-source voltage overshoot in the inductive load standard pulse test. On the other hand reliable circuit operation requires an assessment of the isolation strength of the thin dielectric layer in the main commutation loop, because critical high local electric fields might occur between the pads. Measurements of the dielectric breakdown voltage followed by a statistical failure analysis provide a characteristic life of 14.7 kV and a 10% quantile of 13.5kV in the Weibull fitted data. This characteristic life depends strongly on the ambient temperature and drops to 4.1kV at 125°C. Additionally, ageing tests show an increasing in dielectric breakdown voltage after 500h, 1000h and 2000h at 125°C high-temperature storage due to resin densification processes.
Gallium Nitride (GaN) semiconductor devices are promised to be a good alternative to Silicon (Si) semiconductors in future motor inverters for variable frequency drives (VFDs). They combine low on state resistance and low switching losses with a high blocking voltage capability. Compared to actual inverters based on insulated gate bipolar transistors (IGBTs) the pulse width modulation (PWM) frequency for efficient operation can be increased by a factor of 5 to 10, extending the PWM frequency range up to 500 kHz. This allows the use of motor filters with small component size. As a result, high motor efficiency, low torque ripple, high control bandwidth and nearly ideal sinusoidal output voltages are achieved. Therefore this inverters can be used for high speed spindle motors and dynamic servo drives. This paper focus on the design of a hybrid sine wave filter consisting of an analog and a digital part. The filter is optimized to achieve low power loss and high current control bandwidth. A 3-phase GaN motor inverter operating at 200 kHz PWM frequency at 400 V DC-link voltage verifies the system design.
A gate drive circuit for gallium nitride (GaN) enhancement mode (e-mode) transistors is presented, which avoids parasitic turn-on of the power devices in the halfbridge configuration. New e-mode GaN devices turn on at very low threshold voltages between 1V and 2V. This makes the transistors highly sensitive to spurious turn-on and thus reduces the required safety margin of the gate drive signals. To avoid this parasitic turn-on, a very low gate loop impedance is required. This prevents the halfbridge against bridge shorts during the switching events and guarantees stable gate drive control with increased switching efficiency. The new gate drive circuit is developed in a SPICE simulation environment and verified in a prototype setup by a double pulse test. The simulation matches very well with the experimental result and demonstrates the suppression of parasitic semiconductor turn-on with the proposed gate drive. Furthermore the dissipated switching energy is reduced, compared to a standard gate drive circuit. High DCDC converter efficiency of 98.67% at 1kW output power is achieved by using the driving circuit for a buck converter prototype with 200kHz switching frequency.
Increasing the switching frequency has been one of the most beneficial advancements in modern power electronics. This trend has been enabled by progress in power semiconductors resulting in increased power densities, efficiencies and control dynamics. The aim of this study is to analyze the influence of three different circuit carrier technologies on switching power loss of 650 V hardswitching GaN devices. Limitations and solutions for half-bridge circuits operating at MHz-switching are investigated by modeling and experiments on a prototype.
An accurate SPICE model is proposed in this paper to calculate the power losses of high voltage converter systems. This supports power circuit optimization in the very first design stage. The parasitic package inductances and the nonlinear voltage dependent semiconductor capacitances are taken into account. In addition the high frequency behavior of the power inductor is investigated. A detailed loss breakdown is done to analyze the main sources of power loss and their physical reasons. The simulation results of the converter waveforms and of its efficiency match very well to the experimental results. The prototype boost converter shows a top efficiency greater than 98.3 % at a switching frequency of 1 MHz and an output voltage of 400 V at the maximum output power of 1 kW.
A Parametric Layout Study of Radiated Emission from High-Frequency Half-Bridge Switching Cells
(2016)
We present a numerical modeling study of radiated emission from half-bridge switching cells based on the method of moments (MoM). A low loop inductance cell design enables high-speed switching of power semiconductors which is demonstrated on a prototype circuit. The layout is further optimized for low radiated emission by variation of the heat sink placement. This is achieved by the heat sink attached to the phase terminal. The performance of the structure in terms of loop impedance, electric field radiation and sensitivity to cable attachments are numerically studied. Emission peaks arising from loop resonances can be reduced by over 20 dB with damping elements in the switching cell. The improved EMI performance of the proposed structure is attributed to decoupling of the loop current from the heat sink structure.
Recent development of GaN power transistors with blocking voltages up to 650V enables novel power electronics applications with outstanding performance in high-frequency operation. This paper demonstrates a class E power amplifier with 13.56MHz switching frequency for inductively coupled DC power supplies. Continuous wave output power up to 200W is achieved with 95% Power Added Efficiency (PAE).