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Design of a Low Multi-Loop Inductance Three Level Neutral Point Clamped Converter with GaN HEMTs
(2020)
This work shows a numerical and experimental analysis of a Neutral-Point-Clamp (NPC) three level inverter featuring an ultra low inductance printed circuit board (PCB) design in consideration of the mutual inductive and capacitive couplings. The commutation loops in this design are found to be strongly dependent on the vertical thickness of the used prepregs and the core. For vertical thicknesses ≤ 100 μm capacitive coupling must be taken into account in the switching cell design. Experimental measurements of a test set-up with a total PCB thickness of 400 μm results in commutation loop inductances from 1.4 nH up to 3.1 nH. In this set-up, switching tests without external gate resistor showed only a maximum voltage overshoot of 7% at 800 V. Based on a numerical analysis of the NPC cell we propose a further switching performance improvement with significant smaller parasitic inductance due to the application of novel printed circuit technologies such as the integration of bare dies into the printed circuit board or polyimide as an interlayer dielectric material.
We present a numerical and experimental design study for reducing conducted common mode noise for frequencies below 10MHz generated in switching cells comprising sub-nH commutation loops. Compared to conventional methods of adding external gate resistors our approach does not degrade efficiency. A parallel plate loop design (characterized by a minimum loop inductance and small board area usage) is found suboptimal in terms of conducted EMI compared to a micro-strip line loop geometry. The net ground impedance rather than the net ground inductance is found to mainly contribute to the observed EMI noise.