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Epigenetic modifiers of the histone deacetylase (HDAC) family contribute to autoimmunity, cancer, HIV infection, inflammation, and neurodegeneration. Hence, histone deacetylase inhibitors (HDACi), which alter protein acetylation, gene expression patterns, and cell fate decisions, represent promising new drugs for the therapy of these diseases. Whereas pan-HDACi inhibit all 11 Zn2+-dependent histone deacetylases (HDACs) and cause a broad spectrum of side effects, specific inhibitors of histone deacetylase 6 (HDAC6i) are supposed to have less side effects. We present the synthesis and biological evaluation of Marbostats, novel HDAC6i that contain the hydroxamic acid moiety linked to tetrahydro-β-carboline derivatives. Our lead compound Marbostat-100 is a more potent and more selective HDAC6i than previously established well-characterized compounds in vitro as well as in cells. Moreover, Marbostat-100 is well tolerated by mice and effective against collagen type II induced arthritis. Thus, Marbostat-100 represents a most selective known HDAC6i and the possibility for clinical evaluation of a HDAC isoform-specific drug.
The invention of the internet made the development of intelligent networking of millions of embedded systems possible. This enabled smart buildings, power grids and cities as well as applications in the fields of health, agriculture and industry. These systems frequently perform safety-critical applications and operations. This makes it urgent to protect these sensible systems as effectively as possible. Especially firmware updates are often the weak point in the systems. If unauthorised persons gain access to the system during the update, malware can be injected or sensitive data can be read and stolen. This paper describes the challenges of secure firmware updates. To protect an embedded system from potential attackers, the concepts integrity, authenticity and confidentiality have to be adhered during the update process. Otherwise, there is an increased risk of modifying or reverse engineering the firmware image. Likewise, inadequately protected software can enable the installation of third-party firmware as well as the installation of firmware on a third-party system. Threat prevention is presented with solutions derived from functional safety and IT security. Aspects of protection against errors in the transmission of updates and against attacks aiming to compromise the system are explained. Finally, a possible sequence of a secure update process is examined in detail for a real embedded system implementation. For this purpose, the preparation, transmission and installation of a firmware update in the bootloader are discussed
The requirements for safety-related software systems increases rapidly. To detect arbitrary hardware faults, there are applicable coding mechanism, that add redundancy to the software. In this way it is possible to replace conventional multi-channel hardware and so reduce costs. Arithmetic codes are one possibility of coded processing and are used in this approach. A further approach to increase fault tolerance is the multiple execution of certain critical parts of software. This kind of time redundancy is easily realized by the parallel processing in an operating system. Faults in the program flow can be monitored. No special compilers, that insert additional generated code into the existing program, are required. The usage of multi-core processors would further increase the performance of such multi-channel software systems. In this paper we present the approach of program flow monitoring combined with coded processing, which is encapsulated in a library of coded data types. The program flow monitoring is indirectly realized by means of an operating system.
We address a novel probabilistic approach to estimate the Worst Case Response Time boundaries of tasks. Multi-core real-time systems process tasks in parallel on two or more cores. Tasks in our contribution may preempt other tasks, block tasks with semaphores to access global shared resources, or migrate to another core. The depicted task behavior is random. The shape of collected response times of a task within a processing time is multimodal. Extreme Value approaches need unimodal response time distributions to estimate the Worst Case Response Time of tasks. The new proposed method derives a set of three task set shapes from the source task set. It is used to minimize the uncertainty of random task behavior by maximizing the coverage of possible Worst Case Response Times. The case study evaluates the new proposed estimation method by the use of dynamically generated random tasks with varying task properties.
In this paper we present simulation and model based approaches for evaluating and validating the temporal and safety relevant properties of software intensive safety-critical real-time embedded systems. A high level reliability model of a safe task execution is described by a continuous-time Markov process, enhanced by the modeling of execution times. It is shown that the behavior - regarding real-time and safety metrics - of this theoretical model can be transferred into an abstract system timing model, which then can be analyzed by a discrete event simulation approach. The verification of the discrete event simulation by Markov models offers the possibility of a holistic approach for reliability analysis combined with schedulability analysis of complex safety-critical multicore real-time systems by the discrete event simulation.
Error detecting and correcting codes are widely used in data transmission, storage systems and also for data processing. In logical circuits like arithmetic operations, arbitrary faults can cause errors in the result. However in safety critical applications, it is important to avoid those errors which would lead to system failures. Several approaches are known to protect the result of operations during software processing. In the same way like transmission systems, coded processing uses codes for fault detection. But in contrast to transmission systems, there is no adequate channel model available which makes it possible to evaluate the residue error probability of an arithmetic operation in an analytical way. This paper tries to close the gap of arithmetic error models by the development of a model for an ordinary addition in a computer system. Thus, the reliability of an addition's result can be analytically evaluated.
The data flow is a crucial part of software execution in recent applications. It depends on the concrete implementation of the realized algorithm and it influences the correctness of a result in case of hardware faults during the calculation. In logical circuits, like arithmetic operations in a processor system, arbitrary faults become a more tremendous aspect in future. With modern manufacturing processes, the probability of such faults will increase and the result of a software's data flow will be more vulnerable. This paper shows a principle evaluation method for the reliability of a software's data flow with arbitrary soft errors also with the concept of fault compensation. This evaluation is discussed by means of a simple example based on an addition.
We present a simulation-based approach to reliability analysis combined with a schedulability analysis of software intensive embedded real-time systems. In such a system not only does the software execution have to be hardened against soft errors, e.g., by means of coded processing or diverse execution, but also the real-time requirements have still to be met in the presence of such error to guarantee a safe operation of the system. For that reason, the influence regarding the real-time characteristics of a given sporadic error with a certain error rate is analyzed by means of a Monte Carlo simulation. Different safety design patterns are introduced and compared. Furthermore, the impact on the schedulability of an embedded system is discussed.
This paper presents the reliability evaluation of task execution during safe software processing. The standard method of duplication in a safety-critical application can also be applied for tasks in a software system. But in addition to this, there is also the possibility for coded task processing to increase the reliability and availability of software. The presented analysis covers the reliability analysis of a single, a duplicated and a coded task by the technique of continuous time Markov processes. Markov processes are often used for the reliability evaluation of safety-critical systems. We introduce a method to describe the execution time of tasks by means of enhanced Markov models and their solution by numerical methods.
In logical circuits, like arithmetic operations in a processor system, arbitrary faults become a more tremendous aspect in future. Modern manufacturing processes lead to less reliability and higher vulnerability of software execution to soft-errors. The correctness of certain results is important especially for safety–critical applications whose reliability depends on the fault-free execution of each single instruction and the dependencies between them. The more complex a software is the more unreliable the outcome is. But, there is a contrary effect. If the probability for multiple faults increases, there is also the chance that two faults compensate each other and the result is correct again. This paper presents the basic ideas for such a reliability evaluation of a software's data flow with arbitrary soft-errors and the effect of fault compensation. Further, this evaluation provides a possibility to compare different implementations of a data flow with respect to the reliability. This is shown by the comparison of two different error codes as alternatives for coded data processing.
In this paper we present a scheduling approach for safety critical, fault tolerant, multicore real-time embedded systems. For this kind of systems, not only the correctness of a computed result but also the strict adherence to timing requirements of computation is essential to avoid any kind of damage. To react to unpredictable, arbitrary hardware faults suitable error detection mechanisms have to be applied. The caused error itself and the detection and correction have great impact on the system's timing behavior. To still keep the real-time requirements, the used scheduling algorithm has to ensure maximum flexibility to disturbances of the timing. The group of Proportionate Fair (Pfairness) multicore scheduling algorithms has been proven to create an optimal schedule in polynomial time. The contribution of this paper is a Pfair-based algorithm that uses tight coupling between the error detection mechanisms and the scheduler of the real-time operating system to establish a loop-back connection.