Refine
Year of publication
Document Type
Is part of the Bibliography
- no (26)
Keywords
- reliability analysis (3)
- error probability (2)
- Animals (1)
- Bootloader (1)
- Cryptograph (1)
- Embedded systems (1)
- Erlang-distribution (1)
- Firmware Update (1)
- IoT (1)
- Markov model (1)
Institute
- Fakultät Elektro- und Informationstechnik (24)
- Laboratory for Safe and Secure Systems (LAS3) (23)
- Labor Industrielle Elektronik (8)
- Research Center of Biomedical Engineering - RCBE (2)
- Fakultät Maschinenbau (1)
- Hochschulleitung/Hochschulverwaltung (1)
- Labor Datenkommunikation (1)
- Zentrum für Forschung und Transfer (ZFT ab 2024; vorher: IAFW) (1)
Begutachtungsstatus
- peer-reviewed (3)
Forschungsbericht 2015
(2015)
The invention of the internet made the development of intelligent networking of millions of embedded systems possible. This enabled smart buildings, power grids and cities as well as applications in the fields of health, agriculture and industry. These systems frequently perform safety-critical applications and operations. This makes it urgent to protect these sensible systems as effectively as possible. Especially firmware updates are often the weak point in the systems. If unauthorised persons gain access to the system during the update, malware can be injected or sensitive data can be read and stolen. This paper describes the challenges of secure firmware updates. To protect an embedded system from potential attackers, the concepts integrity, authenticity and confidentiality have to be adhered during the update process. Otherwise, there is an increased risk of modifying or reverse engineering the firmware image. Likewise, inadequately protected software can enable the installation of third-party firmware as well as the installation of firmware on a third-party system. Threat prevention is presented with solutions derived from functional safety and IT security. Aspects of protection against errors in the transmission of updates and against attacks aiming to compromise the system are explained. Finally, a possible sequence of a secure update process is examined in detail for a real embedded system implementation. For this purpose, the preparation, transmission and installation of a firmware update in the bootloader are discussed
Epigenetic modifiers of the histone deacetylase (HDAC) family contribute to autoimmunity, cancer, HIV infection, inflammation, and neurodegeneration. Hence, histone deacetylase inhibitors (HDACi), which alter protein acetylation, gene expression patterns, and cell fate decisions, represent promising new drugs for the therapy of these diseases. Whereas pan-HDACi inhibit all 11 Zn2+-dependent histone deacetylases (HDACs) and cause a broad spectrum of side effects, specific inhibitors of histone deacetylase 6 (HDAC6i) are supposed to have less side effects. We present the synthesis and biological evaluation of Marbostats, novel HDAC6i that contain the hydroxamic acid moiety linked to tetrahydro-β-carboline derivatives. Our lead compound Marbostat-100 is a more potent and more selective HDAC6i than previously established well-characterized compounds in vitro as well as in cells. Moreover, Marbostat-100 is well tolerated by mice and effective against collagen type II induced arthritis. Thus, Marbostat-100 represents a most selective known HDAC6i and the possibility for clinical evaluation of a HDAC isoform-specific drug.
We present a simulation-based approach to reliability analysis combined with a schedulability analysis of software intensive embedded real-time systems. In such a system not only does the software execution have to be hardened against soft errors, e.g., by means of coded processing or diverse execution, but also the real-time requirements have still to be met in the presence of such error to guarantee a safe operation of the system. For that reason, the influence regarding the real-time characteristics of a given sporadic error with a certain error rate is analyzed by means of a Monte Carlo simulation. Different safety design patterns are introduced and compared. Furthermore, the impact on the schedulability of an embedded system is discussed.
We present a transformation rule to convert linear codes into arithmetic codes. Linear codes are usually used for error detection and correction in broadcast and storage systems. In contrast, arithmetic codes are very suitable for protection of software processing in computer systems. This paper shows how to transform linear codes protecting the data stored in a computer system into arithmetic codes safeguarding the operations built on this data. Combination of the advantages of both coding mechanisms will increase the error detection capability in safety critical applications for embedded systems by detection and correction of arbitrary hardware faults.
In this paper we present simulation and model based approaches for evaluating and validating the temporal and safety relevant properties of software intensive safety-critical real-time embedded systems. A high level reliability model of a safe task execution is described by a continuous-time Markov process, enhanced by the modeling of execution times. It is shown that the behavior - regarding real-time and safety metrics - of this theoretical model can be transferred into an abstract system timing model, which then can be analyzed by a discrete event simulation approach. The verification of the discrete event simulation by Markov models offers the possibility of a holistic approach for reliability analysis combined with schedulability analysis of complex safety-critical multicore real-time systems by the discrete event simulation.
Error detecting and correcting codes are widely used in data transmission, storage systems and also for data processing. In logical circuits like arithmetic operations, arbitrary faults can cause errors in the result. However in safety critical applications, it is important to avoid those errors which would lead to system failures. Several approaches are known to protect the result of operations during software processing. In the same way like transmission systems, coded processing uses codes for fault detection. But in contrast to transmission systems, there is no adequate channel model available which makes it possible to evaluate the residue error probability of an arithmetic operation in an analytical way. This paper tries to close the gap of arithmetic error models by the development of a model for an ordinary addition in a computer system. Thus, the reliability of an addition's result can be analytically evaluated.
