TY - JOUR A1 - Scharfenberg, Georg A1 - Mottok, Jürgen A1 - Artmann, Christina A1 - Hobelsberger, Martin A1 - Paric, Ivan A1 - Großmann, Benjamin A1 - Pohlt, Clemens A1 - Wackerbarth, Alena A1 - Pausch, Uli A1 - Heidrich, Christiane A1 - Fadanelli, Martin A1 - Elsner, Michael A1 - Pöcher, Daniel A1 - Pittroff, Lenz A1 - Beer, Stefan A1 - Brückl, Oliver A1 - Haslbeck, Matthias A1 - Sterner, Michael A1 - Thema, Martin A1 - Muggenthaler, Nicole A1 - Lenck, Thorsten A1 - Götz, Philipp A1 - Eckert, Fabian A1 - Deubzer, Michael A1 - Stingl, Armin A1 - Simsek, Erol A1 - Krämer, Stefan A1 - Großmann, Benjamin A1 - Schlegl, Thomas A1 - Niedersteiner, Sascha A1 - Berlehner, Thomas A1 - Joblin, Mitchell A1 - Mauerer, Wolfgang A1 - Apel, Sven A1 - Siegmund, Janet A1 - Riehle, Dirk A1 - Weber, Joachim A1 - Palm, Christoph A1 - Zobel, Martin A1 - Al-Falouji, Ghassan A1 - Prestel, Dietmar A1 - Scharfenberg, Georg A1 - Mandl, Roland A1 - Deinzer, Arnulf A1 - Halang, W. A1 - Margraf-Stiksrud, Jutta A1 - Sick, Bernhard A1 - Deinzer, Renate A1 - Scherzinger, Stefanie A1 - Klettke, Meike A1 - Störl, Uta A1 - Wiech, Katharina A1 - Kubata, Christoph A1 - Sindersberger, Dirk A1 - Monkman, Gareth J. A1 - Dollinger, Markus A1 - Dembianny, Sven A1 - Kölbl, Andreas A1 - Welker, Franz A1 - Meier, Matthias A1 - Thumann, Philipp A1 - Swidergal, Krzysztof A1 - Wagner, Marcus A1 - Haug, Sonja A1 - Vernim, Matthias A1 - Seidenstücker, Barbara A1 - Weber, Karsten A1 - Arsan, Christian A1 - Schone, Reinhold A1 - Münder, Johannes A1 - Schroll-Decker, Irmgard A1 - Dillinger, Andrea Elisabeth A1 - Fuchshofer, Rudolf A1 - Monkman, Gareth J. A1 - Shamonin (Chamonine), Mikhail A1 - Geith, Markus A. A1 - Koch, Fabian A1 - Ühlin, Christian A1 - Schratzenstaller, Thomas A1 - Saßmannshausen, Sean Patrick A1 - Auchter, Eberhard A1 - Kriz, Willy A1 - Springer, Othmar A1 - Thumann, Maria A1 - Kusterle, Wolfgang A1 - Obermeier, Andreas A1 - Udalzow, Anton A1 - Schmailzl, Anton A1 - Hierl, Stefan A1 - Langer, Christoph A1 - Schreiner, Rupert ED - Baier, Wolfgang T1 - Forschungsbericht / Ostbayerische Technische Hochschule Regensburg T3 - Forschungsberichte der OTH Regensburg - 2015 Y1 - 2015 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:bvb:898-opus4-13867 SN - 978-3-00-048589-3 CY - Regensburg ER - TY - GEN A1 - Krämer, Stefan T1 - Effects of Arbitrary Hardware Faults on Multicore Scheduling in Safety-critical Applications – Evaluation by enhanced Markov models and discrete event simulation T2 - 2014 PESW - The 2nd Prague Embedded Systems Workshop, June 2014 Y1 - 2014 UR - https://pesw.fit.cvut.cz/2014/presentations/pesw2014_Kramer.pdf ER - TY - JOUR A1 - Sellmer, Andreas A1 - Stangl, Hubert A1 - Beyer, Mandy A1 - Grünstein, Elisabeth A1 - Leonhardt, Michel A1 - Pongratz, Herwig A1 - Eichhorn, Emerich A1 - Elz, Sigurd A1 - Striegl, Birgit A1 - Jenei-Lanzl, Zsuzsa A1 - Dove, Stefan A1 - Straub, Rainer H. A1 - Krämer, Oliver H. A1 - Mahboobi, Siavosh T1 - Marbostat-100 Defines a New Class of Potent and Selective Antiinflammatory and Antirheumatic Histone Deacetylase 6 Inhibitors JF - Journal of medicinal chemistry N2 - Epigenetic modifiers of the histone deacetylase (HDAC) family contribute to autoimmunity, cancer, HIV infection, inflammation, and neurodegeneration. Hence, histone deacetylase inhibitors (HDACi), which alter protein acetylation, gene expression patterns, and cell fate decisions, represent promising new drugs for the therapy of these diseases. Whereas pan-HDACi inhibit all 11 Zn2+-dependent histone deacetylases (HDACs) and cause a broad spectrum of side effects, specific inhibitors of histone deacetylase 6 (HDAC6i) are supposed to have less side effects. We present the synthesis and biological evaluation of Marbostats, novel HDAC6i that contain the hydroxamic acid moiety linked to tetrahydro-β-carboline derivatives. Our lead compound Marbostat-100 is a more potent and more selective HDAC6i than previously established well-characterized compounds in vitro as well as in cells. Moreover, Marbostat-100 is well tolerated by mice and effective against collagen type II induced arthritis. Thus, Marbostat-100 represents a most selective known HDAC6i and the possibility for clinical evaluation of a HDAC isoform-specific drug. KW - Animals KW - anti-Inflammatory agent KW - chemical synthesis KW - pharmacology KW - therapeutic use KW - toxicity Y1 - 2018 U6 - https://doi.org/10.1021/acs.jmedchem.7b01593 VL - 61 IS - 8 SP - 3454 EP - 3477 PB - ACS Publications ER - TY - CHAP A1 - Herbold, Florian A1 - Reindl, Andrea A1 - Meier, Hans A1 - Niemetz, Michael A1 - Krämer, Stefan ED - Kubátová, Hana ED - Fišer, Petr ED - Borecký, Jaroslav T1 - Secure Software Updates: Challenges and Solutions for Embedded IoT Systems T2 - Proceedings of the 9th Embedded Systems Workshop: July 1-3, 2021 Horomerice, Czech Republic N2 - The invention of the internet made the development of intelligent networking of millions of embedded systems possible. This enabled smart buildings, power grids and cities as well as applications in the fields of health, agriculture and industry. These systems frequently perform safety-critical applications and operations. This makes it urgent to protect these sensible systems as effectively as possible. Especially firmware updates are often the weak point in the systems. If unauthorised persons gain access to the system during the update, malware can be injected or sensitive data can be read and stolen. This paper describes the challenges of secure firmware updates. To protect an embedded system from potential attackers, the concepts integrity, authenticity and confidentiality have to be adhered during the update process. Otherwise, there is an increased risk of modifying or reverse engineering the firmware image. Likewise, inadequately protected software can enable the installation of third-party firmware as well as the installation of firmware on a third-party system. Threat prevention is presented with solutions derived from functional safety and IT security. Aspects of protection against errors in the transmission of updates and against attacks aiming to compromise the system are explained. Finally, a possible sequence of a secure update process is examined in detail for a real embedded system implementation. For this purpose, the preparation, transmission and installation of a firmware update in the bootloader are discussed KW - Bootloader KW - Cryptograph KW - Embedded systems KW - Firmware Update KW - IoT KW - Safety, Security KW - Software Protection Y1 - 2021 UR - https://www.researchgate.net/publication/354995594_Secure_Software_Updates_Challenges_and_Solutions_for_Embedded_IoT_Systems SN - 978-80-01-06858-8 SP - 5 EP - 13 ER - TY - CHAP A1 - Raab, Peter A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans A1 - Racek, Stanislav T1 - Safe software processing by concurrent execution in a real-time operating system T2 - 16th International Conference on Applied Electronics (AE 2011), 2011, Pilsen, Czech Republic N2 - The requirements for safety-related software systems increases rapidly. To detect arbitrary hardware faults, there are applicable coding mechanism, that add redundancy to the software. In this way it is possible to replace conventional multi-channel hardware and so reduce costs. Arithmetic codes are one possibility of coded processing and are used in this approach. A further approach to increase fault tolerance is the multiple execution of certain critical parts of software. This kind of time redundancy is easily realized by the parallel processing in an operating system. Faults in the program flow can be monitored. No special compilers, that insert additional generated code into the existing program, are required. The usage of multi-core processors would further increase the performance of such multi-channel software systems. In this paper we present the approach of program flow monitoring combined with coded processing, which is encapsulated in a library of coded data types. The program flow monitoring is indirectly realized by means of an operating system. Y1 - 2011 SP - 315 EP - 319 ER - TY - CHAP A1 - Mucha, Matthias A1 - Mottok, Jürgen A1 - Krämer, Stefan T1 - Estimation of Worst Case Response Time Boundaries in Multi-Core Real-Time Systems T2 - 2017 International Conference on Applied Electronics (AE), 5-6 Sept. 2017, Pilsen N2 - We address a novel probabilistic approach to estimate the Worst Case Response Time boundaries of tasks. Multi-core real-time systems process tasks in parallel on two or more cores. Tasks in our contribution may preempt other tasks, block tasks with semaphores to access global shared resources, or migrate to another core. The depicted task behavior is random. The shape of collected response times of a task within a processing time is multimodal. Extreme Value approaches need unimodal response time distributions to estimate the Worst Case Response Time of tasks. The new proposed method derives a set of three task set shapes from the source task set. It is used to minimize the uncertainty of random task behavior by maximizing the coverage of possible Worst Case Response Times. The case study evaluates the new proposed estimation method by the use of dynamically generated random tasks with varying task properties. Y1 - 2017 SN - 978-80-261-0641-8 U6 - https://doi.org/10.23919/ae.2017.8053598 SN - 1803-7232 SP - 1 EP - 6 PB - IEEE ER - TY - CHAP A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans T1 - Modifikation des Taskzustandsmodells des LLREF-Schedulers auf einem Dual-Core-Prozess T2 - Proceedings of the 2nd Embedded Software Engineering Congress, 8. bis 10. Dezember 2009, Sindelfingen Y1 - 2009 SP - 628 EP - 636 ER - TY - CHAP A1 - Krämer, Stefan A1 - Raab, Peter A1 - Mottok, Jürgen A1 - Racek, Stanislav T1 - Comparison of Enhanced Markov Models and Discrete Event Simulation T2 - 17th Euromicro Conference on Digital System Design (DSD), 27-29 August 2014, Verona, Italy N2 - In this paper we present simulation and model based approaches for evaluating and validating the temporal and safety relevant properties of software intensive safety-critical real-time embedded systems. A high level reliability model of a safe task execution is described by a continuous-time Markov process, enhanced by the modeling of execution times. It is shown that the behavior - regarding real-time and safety metrics - of this theoretical model can be transferred into an abstract system timing model, which then can be analyzed by a discrete event simulation approach. The verification of the discrete event simulation by Markov models offers the possibility of a holistic approach for reliability analysis combined with schedulability analysis of complex safety-critical multicore real-time systems by the discrete event simulation. Y1 - 2014 U6 - https://doi.org/10.1109/DSD.2014.42 SP - 591 EP - 598 ER - TY - CHAP A1 - Mottok, Jürgen A1 - Krämer, Stefan A1 - Deubzer, Michael A1 - Hobelsberger, Martin A1 - Martin, Felix T1 - Hardware Based Tracing of Embedded Multi-Core Systems T2 - 4th Applied Research Conference, 5th July 2014, Ingolstadt Y1 - 2014 SN - 978-3-8440-2875-1 ER - TY - CHAP A1 - Raab, Peter A1 - Krämer, Stefan A1 - Mottok, Jürgen T1 - Error Model and the Reliability of Arithmetic Operations T2 - 2013 IEEE EUROCON - International Conference on Computer as a Tool, Zagreb, Croatia, July 1-4, 2013 N2 - Error detecting and correcting codes are widely used in data transmission, storage systems and also for data processing. In logical circuits like arithmetic operations, arbitrary faults can cause errors in the result. However in safety critical applications, it is important to avoid those errors which would lead to system failures. Several approaches are known to protect the result of operations during software processing. In the same way like transmission systems, coded processing uses codes for fault detection. But in contrast to transmission systems, there is no adequate channel model available which makes it possible to evaluate the residue error probability of an arithmetic operation in an analytical way. This paper tries to close the gap of arithmetic error models by the development of a model for an ordinary addition in a computer system. Thus, the reliability of an addition's result can be analytically evaluated. KW - addition KW - channel model KW - coded processing KW - fault simulation KW - Markov model KW - residue error probability Y1 - 2013 U6 - https://doi.org/10.1109/EUROCON.2013.6625047 SP - 630 EP - 637 ER - TY - CHAP A1 - Raab, Peter A1 - Racek, Stanislav A1 - Krämer, Stefan A1 - Mottok, Jürgen T1 - Data Flow Analysis of Software Executed by Unreliable Hardware T2 - 16th Euromicro Conference on Digital System Design, Los Alamitos, CA, USA N2 - The data flow is a crucial part of software execution in recent applications. It depends on the concrete implementation of the realized algorithm and it influences the correctness of a result in case of hardware faults during the calculation. In logical circuits, like arithmetic operations in a processor system, arbitrary faults become a more tremendous aspect in future. With modern manufacturing processes, the probability of such faults will increase and the result of a software's data flow will be more vulnerable. This paper shows a principle evaluation method for the reliability of a software's data flow with arbitrary soft errors also with the concept of fault compensation. This evaluation is discussed by means of a simple example based on an addition. KW - data flow KW - error probability KW - fault compensation KW - reliability analysis KW - software-implemented-hardwarefault-tolerance (SIHFT) Y1 - 2013 U6 - https://doi.org/10.1109/DSD.2013.35 SP - 243 EP - 249 ER - TY - CHAP A1 - Krämer, Stefan A1 - Raab, Peter A1 - Mottok, Jürgen A1 - Racek, Stanislav T1 - Reliability analysis of real-time scheduling by means of stochastic simulation T2 - 2012 International Conference on Applied Electronics (AE 2012), Pilsen, Czech Republic, 5 - 7 September 2012 N2 - We present a simulation-based approach to reliability analysis combined with a schedulability analysis of software intensive embedded real-time systems. In such a system not only does the software execution have to be hardened against soft errors, e.g., by means of coded processing or diverse execution, but also the real-time requirements have still to be met in the presence of such error to guarantee a safe operation of the system. For that reason, the influence regarding the real-time characteristics of a given sporadic error with a certain error rate is analyzed by means of a Monte Carlo simulation. Different safety design patterns are introduced and compared. Furthermore, the impact on the schedulability of an embedded system is discussed. Y1 - 2012 SP - 151 EP - 156 ER - TY - CHAP A1 - Raab, Peter A1 - Racek, Stanislav A1 - Krämer, Stefan A1 - Mottok, Jürgen T1 - Reliability of Task Execution during Safe Software Processing T2 - 15th Euromicro Conference on Digital System Design, Cesme, Turkey N2 - This paper presents the reliability evaluation of task execution during safe software processing. The standard method of duplication in a safety-critical application can also be applied for tasks in a software system. But in addition to this, there is also the possibility for coded task processing to increase the reliability and availability of software. The presented analysis covers the reliability analysis of a single, a duplicated and a coded task by the technique of continuous time Markov processes. Markov processes are often used for the reliability evaluation of safety-critical systems. We introduce a method to describe the execution time of tasks by means of enhanced Markov models and their solution by numerical methods. KW - reliability analysis KW - continuous-time Markov process KW - error probability KW - Erlang-distribution Y1 - 2012 U6 - https://doi.org/10.1109/DSD.2012.110 SP - 84 EP - 89 ER - TY - CHAP A1 - Krämer, Stefan A1 - Raab, Peter A1 - Mottok, Jürgen T1 - Simulationsbasierte Reliability-Analyse – Einflüsse von zufälligen Fehlern auf das Echtzeit-Scheduling T2 - Tagungsband 5th Embedded Software Engineering Kongress, 3. bis 7. Dezember 2012, Sindelfingen Y1 - 2012 SP - 613 EP - 622 ER - TY - JOUR A1 - Raab, Peter A1 - Krämer, Stefan A1 - Mottok, Jürgen T1 - Reliability of data processing and fault compensation in unreliable arithmetic processors, Microprocessors and Microsystems JF - Microprocessors and Microsystems N2 - In logical circuits, like arithmetic operations in a processor system, arbitrary faults become a more tremendous aspect in future. Modern manufacturing processes lead to less reliability and higher vulnerability of software execution to soft-errors. The correctness of certain results is important especially for safety–critical applications whose reliability depends on the fault-free execution of each single instruction and the dependencies between them. The more complex a software is the more unreliable the outcome is. But, there is a contrary effect. If the probability for multiple faults increases, there is also the chance that two faults compensate each other and the result is correct again. This paper presents the basic ideas for such a reliability evaluation of a software's data flow with arbitrary soft-errors and the effect of fault compensation. Further, this evaluation provides a possibility to compare different implementations of a data flow with respect to the reliability. This is shown by the comparison of two different error codes as alternatives for coded data processing. Y1 - 2016 U6 - https://doi.org/10.1016/j.micpro.2015.07.014 VL - 40 IS - Februar SP - 102 EP - 112 PB - Elsevier ER - TY - CHAP A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Racek, Stanislav T1 - Proportionate fair based multicore scheduling for fault tolerant multicore real-time systems T2 - International Conference on Electrical and Information Technologies (ICEIT), 25-27 March 2015, Marakesch, Morocco N2 - In this paper we present a scheduling approach for safety critical, fault tolerant, multicore real-time embedded systems. For this kind of systems, not only the correctness of a computed result but also the strict adherence to timing requirements of computation is essential to avoid any kind of damage. To react to unpredictable, arbitrary hardware faults suitable error detection mechanisms have to be applied. The caused error itself and the detection and correction have great impact on the system's timing behavior. To still keep the real-time requirements, the used scheduling algorithm has to ensure maximum flexibility to disturbances of the timing. The group of Proportionate Fair (Pfairness) multicore scheduling algorithms has been proven to create an optimal schedule in polynomial time. The contribution of this paper is a Pfair-based algorithm that uses tight coupling between the error detection mechanisms and the scheduler of the real-time operating system to establish a loop-back connection. KW - Multicore processing KW - Time factors KW - Safety KW - Schedules KW - Scheduling algorithms KW - Real-time systems Y1 - 2015 U6 - https://doi.org/10.1109/EITech.2015.7162952 SP - 88 EP - 93 ER - TY - CHAP A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans T1 - Modifikation des Taskzustandsmodells des LLREF-Schedulers auf einem Dual-Core-Prozessor T2 - Proceedings of the 2nd Embedded Software Engineering Congress, 8. bis 10. Dezember 2009, Sindelfingen Y1 - 2009 SP - 628 EP - 636 ER - TY - CHAP A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans T1 - Osek-basierende Implementierung des LLREF-Scheduling-Algorithmus für eine Dual-Core-Architektur T2 - 2. Landshuter Symposium Mikrosystemtechnik, Tagungsband, 24. une 25. Februar 2010, Hochschule Landshut Y1 - 2010 SP - 343 EP - 349 ER - TY - CHAP A1 - Raab, Peter A1 - Krämer, Stefan A1 - Mottok, Jürgen T1 - Cyclic codes and error detection during data processing in embedded software systems T2 - Proceedings of the 4rd Embedded Software Engineering Congress (ESE), 5.-9. Dezember 2011, Sindelfingen Y1 - 2011 SP - 577 EP - 590 ER - TY - JOUR A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans T1 - Multi-Core Scheduling in Embedded Systemen, Teil 1 JF - Hanser Automotive Y1 - 2010 IS - 1-2 SP - 18 EP - 22 ER - TY - JOUR A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans T1 - Multi-Core Scheduling in Embedded Systemen, Teil 2 JF - Hanser Automotive Y1 - 2010 IS - 3-4 SP - 23 EP - 25 ER - TY - JOUR A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Meier, Hans T1 - Multi-Core Scheduling in Embedded Systemen, Teil 3 JF - Hanser Automotive Y1 - 2010 IS - 5-6 SP - 14 EP - 16 ER - TY - JOUR A1 - Raab, Peter A1 - Krämer, Stefan A1 - Mottok, Jürgen A1 - Vavricka, Vlastimil T1 - Isomorphism between Linear Codes and Arithmetic Codes for Safe Data Processing in Embedded Software Systems JF - Computing and Informatics (CAI) N2 - We present a transformation rule to convert linear codes into arithmetic codes. Linear codes are usually used for error detection and correction in broadcast and storage systems. In contrast, arithmetic codes are very suitable for protection of software processing in computer systems. This paper shows how to transform linear codes protecting the data stored in a computer system into arithmetic codes safeguarding the operations built on this data. Combination of the advantages of both coding mechanisms will increase the error detection capability in safety critical applications for embedded systems by detection and correction of arbitrary hardware faults. Y1 - 2014 UR - https://pdfs.semanticscholar.org/eb7c/f626eb4dcf33bb9c615d477099188eadc76b.pdf?_ga=2.23977850.1374482597.1614464499-73487869.1612391519 VL - 33 SP - 721 EP - 734 ER - TY - CHAP A1 - Krämer, Stefan A1 - Raab, Peter A1 - Mottok, Jürgen A1 - Racek, Stanislav T1 - Comparison of Enhanced Markov Models and Discrete Event Simulation – for evaluation of probabilistic Faults in safety-critical real-time task sets T2 - Proceedings of EUROMICRO DSD 2014 - 17th Euromicro Conference on Digital System Design N2 - In this paper we present simulation and model based approaches for evaluating and validating the temporal and safety relevant properties of software intensive safety-critical real-time embedded systems. A high level reliability model of a safe task execution is described by a continuous-time Markov process, enhanced by the modeling of execution times. It is shown that the behavior - regarding real-time and safety metrics - of this theoretical model can be transferred into an abstract system timing model, which then can be analyzed by a discrete event simulation approach. The verification of the discrete event simulation by Markov models offers the possibility of a holistic approach for reliability analysis combined with schedulability analysis of complex safety-critical multicore real-time systems by the discrete event simulation. KW - Model KW - Stochastic simulation KW - reliability analysis KW - safe software processing KW - real-time operating system KW - multicore scheduling KW - discrete event simulation KW - fault injection Y1 - 2014 U6 - https://doi.org/10.1109/DSD.2014.42 SP - 591 EP - 598 ER - TY - CHAP A1 - Krämer, Stefan A1 - Simsek, Erol A1 - Braun, Jürgen A1 - Deubzer, Michael A1 - Stingl, Armin A1 - Hobelsberger, Martin A1 - Mottok, Jürgen T1 - Mut zu Fehlern, um die Qualität zu steigern – Fault-Injection zur Steigerung der Zuverlässigkeit T2 - Tagungsband, 6th Embedded Software Engineering, Kongress 2013, 2. bis 6. Dezember 2013, Sindelfingen Y1 - 2013 SN - 978-3-8343-2408-5 SP - 577 EP - 585 ER - TY - CHAP A1 - Seidl, M. A1 - Krämer, Stefan A1 - Mottok, Jürgen T1 - Improving the reliability of an embedded real-time system by applying coded processing T2 - 4th Applied Research Conference, 5th July 2014, Ingolstadt Y1 - 2014 SN - 978-3-8440-2875-1 SP - 70 EP - 74 PB - Shaker CY - Aachen ER -