Test setup for reliability studies of DDR2 SDRAM

  • A DDR2 DRAM test setup is developed and implemented on the Griffin III ATE test system from HILEVEL Technologies. The test system provides a raw platform for performing various mixed signal and digital tests. In order to configure patterns easily in a vector format, a software platform is developed to manage test patterns according to the user's analysis needs. As examples, retention test patterns with disabled self-refresh are applied to 2 Gbit DDR2 SDRAM of two different DRAM vendors. The devices are characterized in respect to their intrinsic leakage and data retention behavior under the influence of stress conditions such as temperature or access algorithm. The tests are automated and test data is logged for an off-line data analysis. Data is recorded before and after solder simulation steps in order to observe a retention time degradation.

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Author:Martin Versen, W. Ernst, P. Gulati, G. Singh
Parent Title (English):Microelectronics Reliability
Document Type:Contribution to a Periodical
Publication Year:2015
Tag:DRAM retention solder simulation; Microelectronics
faculties / departments:Fakultät für Ingenieurwissenschaften
Dewey Decimal Classification:6 Technik, Medizin, angewandte Wissenschaften / 62 Ingenieurwissenschaften / 620 Ingenieurwissenschaften und zugeordnete Tätigkeiten