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The recent developments in power semiconductor devices and increasing demands on reliability as well as on operation performance require innovative package technologies. Such a novel package technique based on a Planar Interconnect Technology (SiPLIT®) for power modules is introduced in this work. This package features thick Cu interconnects on a high-reliable insulating film for power semiconductor chip top contacts. Due to the conductor structure and contact technology, on-resistance and stray inductances are very low compared to state-of-the-art Al wire bonds. In addition, large area contacting improves the power cycling capability and surge current robustness significantly. These remark-able properties have been verified on several prototype modules where the manufacturing process has also been optimised in terms of cost-effectiveness, system integration and maturity for series production.
CdS/CdTe thin film solar technology is one of the most promising concepts to accomplish high efficiencies and low costs in mass production. Further knowledge about electric parameters, such as serial resistances and recombination losses, is needed in order to improve in a systematic approach the module efficiency. The basic tool for device evaluation is the JV-measurement (current density – voltage) under standard test conditions. JVmeasurements result in rather direct determination of electric parameters, and detailed JV-analysis in indirect determination of some more relevant electric parameters. For thin film solar cells the usual 2-diode model and the responsible equation can be reduced to a 1-diode model due to significant recombination processes in the space charge region. However, the fit results suffer on imprecision of derived recombination currents (Jrec), and series resistance (Rs), due to their ambiguousness in fit routine. Direct and precise access of Rs by measurements fails for CdTe, due to its significant dependency on illumination levels. In this work we present a new method for precise Rs and Jrec determination of CdTe cells.
Embedded real-time systems are growing in complexity, which goes far beyond simplistic closed-loop functionality. Current approaches for worst-case execution time (WCET) analysis are used to verify the deadlines of such systems. These approaches calculate or measure the WCET as a single value that is expected as an upper bound for a system’s execution time. Overestimations are taken into account to make this upper bound a safe bound, but modern processor architectures expand those overestimations into unrealistic areas. Therefore, we present in this paper how of safety analysis model probabilities can be combined with elements of system development models to calculate a probabilistic WCET. This approach can be applied to systems that use mechanisms belonging to the area of fault tolerance, since such mechanisms are usually quantified using safety analyses to certify the system as being highly reliable or safe. A tool prototype implementing this approach is also presented which provides reliable safe upper bounds by performing a static WCET analysis and which overcomes the frequently encountered problem of dependence structures by using a fault injection approach.