FG Verteilte Systeme und Betriebssysteme
Refine
Document Type
- Doctoral thesis (7)
- Conference proceeding (4)
- Report (1)
Has Fulltext
- yes (12)
Is part of the Bibliography
- no (12)
Keywords
- Funktionseinheit (3)
- Laufzeit (3)
- Reconfiguration (3)
- Rekonfiguration (3)
- Betriebssystem (2)
- Betriebssysteme (2)
- Eingebettete Systeme (2)
- Eingebettetes System (2)
- Fehlertoleranz (2)
- Fine-grained (2)
Institute
- FG Verteilte Systeme und Betriebssysteme (12) (remove)
Multi- and manycore processors promise to combine high overall peak performance with moderate power consumption to meet the constantly growing demand for computational power under the energy constraints of today’s CMOS technology. Future systems with manycore processors are expected to contain a huge amount of cores, which exceeds the number of processes that will run simultaneously. Consequently, processor time sharing approaches, that introduce significant overhead from regular context switches in common OS, will no longer be necessary.
This work investigates mechanisms for scalable and energy-efficient spatial partitioning of multi- and manycore processor systems. In addition, it explores the implications of exclusive processor core allocation to user processes due to the absence of temporal multiplexing and offers approaches to ease the adaptation to the new programming model.
The proposed mechanisms achieved fast thread allocation which motivates applications for dynamic thread allocation and benefits performance as well as energy efficiency. The efficiency control and resource revocation mechanisms detect and prevent wasteful and inefficient resource occupation from poorly optimized or malicious processes. In this way, the global efficiency of the system is optimized. The dynamic processing resource allocation and revocation handling has been integrated into a task parallel runtime system, to disburden the application programmer from manual implementation and to increase productivity.
Since electronics started to scale down, a growing concern about the reliability of these electronic devices has emerged. At the same time, the increased demand for high performance within the safety- and mixed-critical domains, such as the aerospace and automotive industry, motivated a shift from previous consolidated and mature technology to the new cutting edge devices with smaller feature sizes. Therefore, there is a need to improve the fault tolerance of these high-end devices so that minimum failure rates can be obeyed. Although redundancy has been a great solution for these problems, their drawbacks such as power and area overheads must be watched carefully, so that per-unit price does not extrapolate affordable limits, and the redundancy does not add more sources of error than it improves the fault tolerance. This thesis proposes an approach for run-time management of redundancy among the processor internal Functional Units (FUs) within mixed-critical scenarios, tackling the compensation of the trade-offs between fault-tolerance, power consumption, hardware usage (ageing), and hardware area (cost).
With these objectives in mind, this thesis presents a concept for a dynamic processor architecture capable to enable and disable redundancy of FUs on-demand, and a software mechanism for criticality-aware management of these units for mixed-critical processes within an Operating System (OS). For this purpose, a processor design was extended with a few additional instructions that enabled different replication schemes in the processor at run-time. Furthermore, a compatible Real-Time Operating System (RTOS) is also extended to enable the desired criticality-aware management of units.
Evaluating the implemented test platform when the extended processor was running bare-metal code, the latency to shift between different replication schemes was of only one instructions cycle. Furthermore, when the processor was running the adapted RTOS, the run-time overhead over the latency to switch between processes remained below 2.5%. Meanwhile, resulting from the processor extensions, the hardware overhead remained smaller than standard full core replication schemes such as core lock-step approaches. Regarding fault tolerance, the expected failure rate of the FUs module decreased by approximately 80% when its FUs were configured with Triple Modular Redundancy (TMR). Furthermore, when considering the whole area of the processor core, its respective failure rate decreased by about 15% when configured these units with the same triplication scheme. Finally, it is also presented that the run-time management of FUs was likewise able to decrease the power consumption and hardware ageing for the proposed mixed-critical scenario. After all, we can say that the concept can increase fault tolerance on-demand of a processor design with moderately low hardware overhead, while it also minimises the power consumption and hardware usage (ageing) for its intended mixed-critical scenario.
As the architectural walls drive the number of parallel cores in multicore systems up, it becomes harder to maintain cache coherence across all of the physical memory and all cores. On the other hand, even given a performant cache-coherent system, the unavoidable non-uniform memory (NUMA) and non-uniform cache (NUCA) architectures make programming for it difficult.
A potential solution to this problem is to interpret massive multicore machines as a distributed system with remote memory access, and therefore, use existing distributed programming models. A natural fit for such an approach is the PGAS model, which provides a global address space divided into partitions that can be either local or remote. Unfortunately, completely discarding the notion of sharing ignores the efficient hardware mechanisms available in multicore machines with shared memory.
This survey examines PGAS frameworks and communication libraries with an focus on the PGAS model to enable PGAS applications to exploit shared memory in massive multicore machines without sacrificing the benefits of the PGAS programming model.
In the last 30 years, communication became one of the most important pillars of our civilization. Every day terabytes of information are moved wired and wireless between computers. In order to transport this amount of data, researchers and industry increase the data rates of the underlying communication networks with impressive speed. However, such ultra-high data rates are unavailable at the communication endpoints.
One reason why ultra-high data rates are still not available for the communication endpoints is their inability to handle the protocol processing at this data rate. In order to enable communication endpoints to process high-volume data streams, the protocol processing has to be parallelized and optimized on all processing levels. However, parallelization and optimization are cumbersome tasks, which are further complicated as the protocol processing is traditionally carried out by the operating system.
This thesis aims at circumventing these problems by moving the protocol processing into external processing hardware and interpreting communication protocols as stream processing problems. In order to achieve ultra-high data rates at the communication endpoints, a protocol stream processing design approach was developed and evaluated. The design process is separated into implementation, soft real-time analysis, parallelization, and mapping steps, which allow a scalable protocol implementation without paradigm changes. Furthermore, a data link protocol for 100 Gbit/s wireless was developed and implemented with the new stream processing design concept, in order to show its feasibility. The data link protocol is configurable for different communication conditions and easy to parallelize by providing different granularities of packets. The proposed design-process has shown to be suitable for uncovering bottlenecks and helping with debugging the individual stages of the protocol.
The tiny logic elements in modern integrated circuits increase the rate of transient failures significantly. Therefore, redundancy on various levels is necessary to retain reliability. However, for mixed-criticality scenarios, the typical processor designs offer either too little fault-tolerance or too much redundancy for one part of the applications. Amongst others, we specifically address redundant processor internal functional units (FU) to cope with transient errors and support wear leveling. A real-time operating system (RTOS) was extended to control our prototypical hardware platform and, since it can be configured deterministically within few clock cycles, we are able to reconfigure the FUs dynamically, at process switching time, according to the specified critically of the running processes. Our mechanisms were integrated into the Plasma processor and the Plasma-RTOS. With few changes to the original software code, it was, for example, possible to quickly change from fault-detecting to fault-correcting modes of the processor on demand.
System reconfiguration of hardware resources has been done in multiple system domains. Such systems are usually found in the context of FPGAs, where reconfiguration is done usually over its primitives (e.g., LUTs, Flip-Flops). Or even in the context of MPSoC designs, where core management (e.g., lock-step operation in multi-core designs) is the most used approach. However, recent works have shown that configuration at Functional Units (FUs) granularity might come with benefits. For example, it can increase the configuration space due to its finer granularity, and, as a consequence, the options to deal with problems (e.g., due to aging) in the units itself. Within this context, this paper presents a system capable to configure its FUs (e.g., ALUs, multipliers, dividers) into different operation modes. The system uses an Operating System to control HW reconfiguration during process switching time and takes into account the health state of its units in a mixed-criticality applications scenario. Results show that, within this scenario, the system is able to reconfigure itself accomplishing health state modifications of its HW elements.
The strive for performance, low power consumption, and less chip area have been diminishing the reliability and the time to fault occurrences due to wear out of electronic devices. Recent research has shown that functional units within processors usually execute a different amount of operations when running programs. Therefore, these units present different individual wear out during their lifetime. Most existent schemes for re-configuration of processors due to fault detection and other processor parameters are done at the level of cores which is a costly way to achieve redundancy. This paper presents a low latency (approximately 1 clock cycle) software controlled mechanism to reconfigure units within processor cores according to predefined parameters. Such reconfiguration capability delivers features like wear out balance of processor functional units, configuration of units according to the criticality of tasks running on an operating system and configurations to gain in performance (e.g. parallel execution) when possible. The focus of this paper is to show the implemented low latency reconfiguration mechanism and highlight its possible main features.
Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on-line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system.
For decades, there has been a distinction between fast, volatile and slow, non-volatile memory technologies in the storage hierarchy of computer systems. While volatile memories offer a byte addressable interface, persistence was limited to slower, block-oriented media. As a consequence, processing and storing information implies copying data from the persistent storage to volatile memory and vice versa.
In recent years, a new memory technology which is both byte-addressable and non-volatile has been announced: Non-Volatile Random Access Memory (NVRAM). Its unique combination of features allows processing of information exactly at the location where it is stored permanently, thereby eliminating the need for copies. Without the need to create and manage copies, data can be processed significantly faster.
The processing of persistent information can be disrupted by failures, like crashes. When changes are only partially performed, data might be left in an inconsistent state. Such a situation can be avoided by creating a copy before starting to change data. That backup is restored when a failure has been detected. Such a procedure relies on a highly specific order of its operations, because the backup can only be disposed after all changes have been carried out successfully. Since NVRAM removes the need for accessing block-oriented media, it removes a major bottleneck in the processing of persistent information, especially when only small amounts of data are modified. As a result, controlling the order of operations dominates the processing performance.
This thesis analyses transactional mechanisms for data on NVRAM which can guarantee that sequences of operations are either carried out as one unit or not at all. The idea is based on creating backups, as sketched above. Existing approaches for the traditional storage hierarchy use separate memory locations for backup and modified data. In a first step, the costs of applying existing procedures to NVRAM are identified. Afterwards, a novel approach which couples the versions tighter in space is presented. Enabled by the unique properties of NVRAM, this new approach is able to reduce the costs of ordering. The processing of persistent data can thereby be sped up significantly.
Drahtlose eingebettete Systeme haben vielfältige Anwendungsmöglichkeiten, sei es im Internet der Dinge oder in Sensornetzen. Diese Systeme sollen dabei ohne Eingriff von außen eine hohe Laufzeit erreichen. Die Energieversorgung und der Verbrauch spielen dabei entscheidende Rollen, sind jedoch Varianzen unterworfen. Sollen Wartungsintervalle oder Lebenszeitziele erreicht werden, ist deshalb ein dynamisches Energiemanagement unabdingbar.
In dieser Doktorarbeit wird ein solcher Ansatz vorgestellt, umgesetzt und evaluiert. Im Gegensatz zu existierenden Ansätzen werden Varianzen auf allen drei Ebenen des Managements (Energieversorgung, Energieverbrauch und Energieverwaltung) adressiert. Für die Energieversorgung wird eine Batterieüberwachung vorgestellt, welche eine Steuerung des Verbrauchs ohne komplexe Berechnung des Ladezustands ermöglicht. Der Verbrauch des Systems wird durch einen Software-basierten Ansatz feingranular ermittelt und bezieht Varianzen durch Änderungen der Spannung und der Effizienz von Spannungswandlern ein. Die Verwaltung und Zuordnung der Energie zu Anwendungszielen erfolgt mittels dynamischer Energiebudgets und bietet verschiedene Strategien, um auf Änderungen des Bedarfs adäquat reagieren zu können.
Experiments with wireless sensor networks have shown that unidirectional communication links are quite common. What is even more, they have also shown that the range of a unidirectional link can exceed that of a bidirectional one by far. Still, most of todays routing protocols do not use them, they only eliminate their implications. Those protocols that do use unidirectional links introduce a lot of protocol overhead. One possible conclusion that is often drawn from this fact is that it does not pay to use unidirectional links in a routing protocol. An alternative one is that the overhead produced by the protocols needs to be reduced. This thesis follows the second line of reasoning, and introduces, describes and evaluates five new routing protocols for wireless sensor networks with unidirectional links.
In dieser Arbeit wird ein umfassendes Betriebssystemkonzept für tief eingebettete Steuersysteme vorgestellt. Das Konzept sieht dabei eine vollständig ereignisbasierte Abarbeitung von Aufgaben vor. Nach einer breiten Domänenanalyse wird gezeigt, welche Vorteile der verfolgte Ansatz hinsichtlich der üblichen Randbedingungen der Zielsysteme hat. Außerdem werden praktische Ergebnisse, welche anhand einer exemplarischen Umsetzung des Konzeptes gewonnen wurde, vorgestellt.