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This work addressed the challenges of accurate mm-wave characterization of devices fabricated in advanced semiconductor technologies. It developed the in-situ calibration solution that is easy to be implemented for silicon technologies. The new technique was verified up to 110 GHz on three difference processes: high performance SiGe:C BiCMOS from IHP Microelectronics (Germany), BiCMOS9MMW from STMicroelectronics (France), and RF CMOS 8SF from IBM Microelectronics (USA). The measurement frequency was solely limited by the capability of the test equipment. Practical results demonstrated that proposed in-situ calibration significantly outperforms the convention method independently on the process specifics and complexity. Some important aspects of the on-wafer S-parameter measurement assurance were presented as well. The discussion included the analysis of the calibration residual errors caused by the improper boundary conditions of coplanar calibration standards and the impact of the RF probe tip design. In conclusion, some suggestions for further accuracy improvement of the proposed method are given.
The sensitivity of application-specific integrated circuits (ASICs) to single event effects (SEE) can lead to failures of subsystems which are exposed to increased radiation levels in space and on the ground. The work described in this thesis presents a design methodology for a fully fault-tolerant ASIC that is immune to single event upset effects (SEU) in sequential logic, single event transient effects (SET) in combinatorial logic, and single event latchup effects (SEL). Redundant circuits combined with SEL power switches (SPS) are the basis for a design methodology which achieves this goal. Within the standard ASIC design flow enhancements were made in order to incorporate redundancy and SPS cells and, consequently, enable protection against SEU, SET, and SEL. In order to validate the resulting fault-tolerant circuits a fault-injection environment with carefully designed fault models was developed. The moments of fault occurrence and their durations are modeled according to the real effects in actual hardware. The proposed design methodology was applied to an innovative space craft area network (SCAN) central processor unit, known as middleware switch processor. The measurement results presented in this thesis prove the correct functionality of DMR and SPS circuits, as well as the high fault-tolerance of the implemented ASICs along with moderate overhead with respect to power consumption and occupied silicon area. Irradiation measurements demonstrated the correct design and successful implementation of the SPS cell.