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Energy efficiency is vital for future low-power electronic applications. This ultra-low power consumption requirement enables the research beyond the conventional charge-based memories. Further, reliability, high scalability, fast switching, CMOS compatibility, high endurance, etc., are some of the characteristics envisaged by the new generation of emerging non-volatile memories (NVMs). A memristor or OxRAM is one among the many emerging NVMs, which can exhibit the aforementioned characteristics, and it has the potential to replace the power-hungry conventional NVMs.
The memristive devices have the advantage of monolithic integration with the CMOS logic, which enables the widening of their application areas. Despite their various advantages, the reliability, forming voltages, and variability of the devices pose a hurdle to their wide commercial usage. Hence, it is crucial to identify these factors and mitigate them. This thesis addresses these issues through fabrication process improvements, electrical characterization techniques, and device-engineering methods.
The improvements in the fabrication processes reduced the pristine state currents of the memristive devices. It impacted the reliability and resistive switching performance of the memristive devices directly. To further improve the performance, the memristive devices are integrated into the 130 nm BiCMOS baseline technology of IHP. Additionally, dedicated test structures are developed to monitor and control the fabrication process steps through in-line electrical characterization.
Further, the forming current and voltage values, along with their dispersions in the 4 kbit memristive arrays, were reduced by utilizing the electrical characterization techniques. Accordingly, the forming operations were performed at high operating temperatures using incremental step pulse and verify algorithm (ISPVA). In contrast to the well-known method of increasing the current compliance (1R) or the gate voltage of the transistor (1T-1R) to increase the conduction filament size, a thin layer of Al2O3 is added. This device engineering technique reduced the variability in both LRS and HRS currents of the memristive devices. Additionally, the conduction filament properties in both states are modeled by using the quantum point contact (QPC) model. Finally, harnessing the intrinsic variability of the memristive devices for neuromorphic computing applications is demonstrated. The reliability of the devices is assessed through endurance and retention characteristics.
Conventional semiconductor memories are facing many challenges concerning their yield, reliability, testability, and manufacturability as the feature size decreases. Although they are used in the vast majority of electronic devices, their applicability for upcoming digital systems is questionable. On the other hand, due to unprecedented development of mobile devices even faster, denser, and more power-efficient semiconductor memories are required. As a consequence, many researchers and system designers are seeking new memory solutions. The greatest attention is paid to solid-state, non-volatile memories (NVMs) such as PCRAMs, MRAMs/STT-MRAMs, FeRAMs, and RRAMs. Due to their promising features like non-volatility, low-power consumption, and great scalability they are expected to meet the challenging demands of future digital systems.
Unfortunately, despite all advantages they offer, emerging NVMs pose some peculiar characteristics like limited endurance, variable data retention time, or vulnerability to external factors. On top of that, they are still in early-maturity state where their fabrication processes are not of high quality and are prone to high variations. Because of that, emerging NVMs may suffer from permanent faults which can occur right after production or in the field, during their operational time. As a consequence, the reliability of new memory technologies requires special management and great improvement.
The thesis introduces system-level approach aimed at comprehensive reliability management of existing and emerging NVMs. It presents novel on-line repair techniques which focus on specific issues of NVMs. The block-level repair manages post-production faults in the memory array. The word-level repair aims at hard faults caused by wear-out memory cells. Finally, the error-correcting code with increased hard-error correction capability handles soft and hard errors in the memory array.
Because proposed techniques are based on similar principles, they can be combined into a consistent system. Depending on the way how they are connected, different repair schemes can be achieved. Moreover, by merging them into the system a synergistic effect can be produced where the achieved memory reliability improvement is greater than the sum of reliability improvements achieved with their standalone implementations.
Further in the thesis, such a consistent repair system is presented. Next, its effectiveness, repair capabilities, and applicability for an embedded system are evaluated. In addition, the achieved synergistic effect is described and quantified