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With scaling technology, the nominal I/O voltage of standard transistors has been reduced from 5.0 V in 0.25-um processes to 2.5 V in 65-nm. However, the supply voltages of some applications cannot be reduced at the same rate as that of shrinking technologies. Since high-voltage (HV-) compatible transistors are not available for some recent technologies and need time to be designed after developing a new process technology, designing HV-circuits based on stacked transistors has better benefits because such circuits offer technology independence and full integration with digital circuits to provide system on-chip solutions. However, the HV-circuits, especially HV-drivers, which are used for switching circuits, have a low efficiency because of the high on-resistance resulted by the stacked transistors.
Therefore, the main goal of this work is to design HV-drivers with a minimum on- resistance. To achieve this goal, initially, the gate voltage of each N-stacked transistor is calculated for driving the maximum current in the pull-up and pull-down paths of the HV-driver for various supply voltages. This calculation is performed using the computer algebra system MAXIMA. Regarding the results, which are presented in mathematical formulae, a circuit design methodology is presented to design a circuit to provide the required gate voltage of the each stacked nMOS or pMOS transistor of an HV-driver. Based on this design methodology, a 2-stacked and a 3-stacked CMOS HV-driver is designed in 65-nm TSMC with I/O standard transistors with a nominal voltage of 2.5 V. The simulation results show that the provided gate voltages track approximately the ideal values. In comparison to prior work, the pull-up on-resistances of these HV-drivers are improved about 36% for the maximum allowed supply voltages of 5.0 V and 7.5 V and the pull-down on-resistances have an improvement of 40% and 46%, respectively. For switching a buck converter, the designed 3-stacked CMOS HV-driver is optimised by increasing the number of transistors in each stack. The circuit defined as 3HVDv1 with an area of about 0.187 mm2 is implemented and fabricated on chips using two different package technologies: chip-in-package and chip-on-board. The parasitic effects of bond wires and packaging are discussed in detail.
In addition to this main goal, 3- and a 4-stacked CMOS HV-drivers, 3HVDv2 and 4HVDv3, are designed in view of the drawbacks identified during the design, implementation, simulations and measurements; however, the second design (4HVDv3) is an improved form of the first one (3HVDv2). This HV-driver, 4HVDv3, has improved benefits compared to the other designed circuits and also the common HV-drivers, because it can be applied for supply voltages ranging from 3.5 V to 7.5 V. This range is extended by 66%; no reference voltages are required since the regulating of the stacked main transistors is achieved by using a self-biasing cascade method.