Parallelizing the Dual Simplex Method
Please always quote using this URN: urn:nbn:de:0297-zib-2112
- We study the parallelization of the steepest-edge version of the dual simplex algorithm. Three different parallel implementations are examined, each of which is derived from the CPLEX dual simplex implementation. One alternative uses PVM, one general-purpose System V shared-memory constructs, and one the PowerC extension of C on a Silicon Graphics multi-processor. These versions were tested on different parallel platforms, including heterogeneous workstation clusters, Sun S20-502, Silicon Graphics multi-processors, and an IBM SP2. We report on our computational experience.
Author: | Robert E. Bixby, Alexander Martin |
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Document Type: | ZIB-Report |
Date of first Publication: | 1996/01/19 |
Series (Serial Number): | ZIB-Report (SC-95-45) |
ZIB-Reportnumber: | SC-95-45 |
Published in: | Appeared in: INFORMS Journal on Computing, 12(1), (2000) 45-56 |