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Thermo-mechanical and electromagnetic simulations of a Half-Bridge Insulated Prepackage for Modular Power Modules

  • Wide bandgap semiconductors, SiC and GaN-based power devices represent key candidates in the development of more efficient devices due to their superior electrical and thermal properties compared to silicon. To achieve maximal performance from WBG semiconductors, new packaging technologies and thermo-electric designs must be developed to ensure efficient and fast switching of devices while minimizing losses. The paper aims to investigate the thermal and mechanical behavior of new prepackage embedding technologies by finite element simulation. The focus is on insulated substrates including direct bonded copper (DBC) with various dielectrics such as AlN, Al 2O 3, Si3N 4 and new insulated metal substrates (IMS) with emphasis on commercially available materials and thicknesses. This study proposes a thermo-mechanical pareto-optimization methodology able to identify the best substrate configuration. The sintered silver layer (in both sides of the chip), which is the most prone to failure due to delamination, has been modelled with aWide bandgap semiconductors, SiC and GaN-based power devices represent key candidates in the development of more efficient devices due to their superior electrical and thermal properties compared to silicon. To achieve maximal performance from WBG semiconductors, new packaging technologies and thermo-electric designs must be developed to ensure efficient and fast switching of devices while minimizing losses. The paper aims to investigate the thermal and mechanical behavior of new prepackage embedding technologies by finite element simulation. The focus is on insulated substrates including direct bonded copper (DBC) with various dielectrics such as AlN, Al 2O 3, Si3N 4 and new insulated metal substrates (IMS) with emphasis on commercially available materials and thicknesses. This study proposes a thermo-mechanical pareto-optimization methodology able to identify the best substrate configuration. The sintered silver layer (in both sides of the chip), which is the most prone to failure due to delamination, has been modelled with a temperature-dependent bilinear hardening model to account for plasticity. Pareto-optimization accounts for the module thermal resistance and the plastic strain or Von Mises Stress in the sintered layer. Results demonstrate that the best candidate from the thermo-mechanical point of view is the DBC with AlN showing a thermal resistance of 0.34 K/W, accumulative plastic strain of 0.18 % and Von Mises stress of 274 MPa. Finally, the parasitic inductance of multiple pre-packages is evaluated to scale the power of the module. Proper design allows to achieve a stray inductance as small as 1.23 nH for two prepackages and 2.85 nH for four prepackages.show moreshow less

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Metadaten
Author:Saimir Froku, Ankit Bhushan Sharma, Till HuesgenORCiD, Andrea Irace, Giovanni A. Salvatore
URL / DOI:https://ieeexplore.ieee.org/document/10564779
Identifier:978-3-8007-6288-0 OPAC HS OPAC extern
Parent Title (English):CIPS 2024 : 13th International Conference on Integrated Power Electronics Systems
Publisher:VDE
Place of publication:Berlin
Document Type:conference proceeding (article)
Conference:CIPS 2024; 13th International Conference on Integrated Power Electronics Systems, 12. - 14. März 2024, Düsseldorf, Germany
Language:English
Date of Publication (online):2024/06/19
Year of first Publication:2024
Article Number:10564779
Number of pages:8 Seiten
First Page:574
Last Page:581
Institutes:Fakultät Elektrotechnik
Dewey Decimal Classification:6 Technik, Medizin, angewandte Wissenschaften / 60 Technik
Research focus:FSP1: Energie
FSP3: Produktion
Publication Lists:Huesgen, Till
Sharma, Ankit Bhushan
Publication reviewed:begutachtet
Release Date:2024/06/28
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