Refine
Document Type
Publication reviewed
- begutachtet (20)
- nicht begutachtet (2)
Keywords
- LILIPUT (7)
- MEDAL (6)
- DrGaN (5)
- GaNmsPEBB (2)
- Halbleiterbauelement (1)
- Leiterplattenembedding (1)
- Sinterpack (1)
- begutachtet (1)
- empsABB (1)
Institute
Das Einbetten von Halbleiterbauelementen stellt einen innovativen Ansatz für die Aufbau- und Verbindungstechnik (AVT) leistungselektronischer Systeme dar. Im Rahmen von zahlreichen Forschungsvorhaben wurde gezeigt, dass im Vergleich zu einer konventionellen AVT geringere parasitäre Induktivitäten und Widerstände [1, 2]und damit geringere Leitungs- und Schaltverluste ermöglicht werden. Auch kann der thermische Widerstand durch den Einsatz von Dickkupfersubstraten und wärmeleitfähigen organischen Isolatoren erheblich reduziert werden [2, 3, 4]. Dadurch lässt sich auf Systemebene eine höher Leistungsdichte erreichen [5], ohne dass dadurch die Lastwechselfestigkeit leidet [6, 3].
Dennoch findet die Technologie bis heute nur im Low-Power Bereich oder zum Chip-Scale Packaging von einzelnen Leistungsschaltern kommerziellen Einsatz.
Dieser Vortrag diskutiert mögliche Hemmnisse und Grenzen der Technologie.
In this work an approach for a direct experimental comparison of the application-oriented performance between two high current GaN DC/DC converters based on 7mΩ, 100V GaN HEMTs in a commercial off-the-shelf top-cooled package and 5mΩ, 100V GaN HEMTs embedded in a thermally-optimized single-chip package is given. The two packaging versions are compared by a maximally identical implementation of the power and gate loops in a 48V, 300kHz buck converter with two parallel GaN HEMTs. In the single-chip package the die is directly mounted on a 12×6mm 2 copper-heat spreader offering a significantly lower thermal resistance to heatsink (1.69KW −1 ) in comparison to the commercial off-the-shelf version (2.45KW −1 ). For a direct benchmark, the COTS-based converter has an identical power-loop to the SCP-version with a novel gate-drive concept. Both versions have an efficiency of 96.8% at 65A output current (output power: 1.5kW), while the commercial off-the-shelf version has a better efficiency for lower currents, due to its better hard-switching Figure-of-Merits and therefore lower switching losses and reaches an output current of up to 80A (output power: 1.75kW). A detailed analytical loss breakdown for the different transistors in dependence of the temperature and output current is given to proof the measured current point, where the efficiencies of both converters are identical, since the higher switching losses of the SCP version are compensated by lower conduction losses at higher currents and temperatures compared to the smaller COTS transistor. Finally, an outlook on further improvements for reaching higher output currents and potential converters for a more fair comparison of different thermally optimized SMD packages are given.
Previously, a novel concept for PCB embedding of power semiconductors with reinforced top contacts has been published by our group. In this work, a thermomechanical study is performed to understand the fracture probability of the chip during fabrication. The ball-on-ring (BOR) and ball-on-edge (BOE) tests are employed to characterize the chip strength. A probabilistic model is used to evaluate the failure probability. The contribution of different fabrication steps to the overall failure probability is investigated. A parametric analysis is performed to analyze the impact of material choice and the thickness of the substrate and the interposer. A single-step sintered package with a 200 μm thick Cu interposer and an 800 μm thick Cu substrate with hard Cu leads to a 12% failure probability compared to 52% for an identical stack with a soft Cu substrate. The top surface failure probability for a 150 μm thick CIC interposer is 0.016% compared to 8.6% for a 100 μm Cu interposer., for an identical 800μm thick Cu substrate. A sinterlamination process, where the die-attach and curing of the prepreg material simultaneously take place, results in a 0.03% failure probability.
PCB embedding is an attractive packaging technology for highly integrated future power systems. Electrical and thermal benefits and limitations are well understood, but only few publications focus on reliability. Here we are addressing high-humidity high temperature reverse bias (H3TRB) tests, which are performed to gain deeper understanding of the limitations of this technology. Cu filament growth is observed on both, PCB embedded samples and silicone potted reference samples. These filaments may form a conductive path and lead to an increased leakage current in blocking mode. Electrochemical corrosion of the Cu-plated guard ring is identified as root cause.
Thermal impedance evaluation of optimized PCB-based GaN HEMT Single-ChipPrepackage using VGS Method
(2022)
This study evaluates the measurement of the thermal resistance and impedance of GaN HEMTs packages with gatesource voltage (VGS) for junction temperature measurement. First, calibration measurement of VGS vs temperature is performed in an oven. Large deviations from chip to chip require that each device is calibrated separately. Zth is measured for an experimental single-chip prepackage (SCP), developed in our lab, and a commercial reference package (GaNpx). The measured junction to ambient thermal resistance of the SCP is 35% lower compared to the reference. This is caused by a copper heat spreader integrated in the package. The thermal resistance of multiple packages attached on one PCB is also performed. This measurement indicates a maximum difference of 35%. This difference remained the same in several experiments with two thermal interface materials and pressure levels.
Thermisch und elektrisch optimiertes Leiterplatten-Prepackage für 100V/100A GaN Leistungshalbleiter
(2021)
In dieser Arbeit wird ein Integrationskonzept für GaN Leistungshalbleiter in Leiterplattentechnologie vorgestellt. Das
Konzept beruht auf thermisch optimierten Prepackages mit integrierten Temperatursensoren, die in Leiterplattenembeddingtechnologie hergestellt werden. Durch ein asymmetrisches Layout wird ein niederinduktiver Kommutierungskreis ermöglicht. Funktionsmuster mit einem 100 V / 120 A GaN HEMT wurden aufgebaut und erprobt. Die Bauteile sind elektrisch voll funktionsfähig und weisen einen thermischen Widerstand von 3,34 K/W auf. Dieser Wert liegt 35% unter dem eines kommerziellen Referenzbauteils.
To make the full performance of the intrinsic 100 V, 5 mΩ gallium nitride transistors available on system level, in this work an asymmetrical & thermally optimized PCB embedded single chip package with integrated resistance thermometer, high temperature capability and a thermal resistance Rth,j−hs of 3.3 K W−1 is characterized in a 48 V to 24 V 300 kHz mild-hybrid DC/DC operation with two paralleled chips in each low- (LS) and high-side (HS). The transistors are mounted on a 4-layer multilayer PCB with 1 mm copper inlays to achieve a high current capability, while allowing narrow logic traces on the same PCB. The designed converter is achieving a light load efficiency of ≥99 % and an efficiency of 97 % at 60 A output current and ≈1.3 kW output power in a 48 V to 24 V 300 kHz buck-converter operation. The on-board temperature readout circuit and the phase output current sensor offer the possibility to extend the GaN transistors to an intelligent power module by the compact and simple sensors.
PCB embedding is a novel and promising approach for packaging of power semiconductors. Due to the planar construction the technology enables lower conduction and switching losses, an increase switching frequency and ultimately yields a higher power density. Usually embedding is performed during lay-up of the PCB. Here, a novel concept for fabrication of PCB based power devices is proposed. The bare dies are sandwiched between two circuit boards using Ag sintering and simultaneous lamination of prepregs. The technology is discussed with reference to a 600V / 50A IGBT half bridge module. Using high-Tg isolator material in the PCB, a suitable process window is established and laboratory demonstrators are fabricated. An electrical characterization proves the feasibility of the concept.
The embedding of power electronics components into the PCB increases their thermal and electrical performance. Due to lower parasitic inductances and a lower thermal resistance, the overall power density of the system can be increased. However, there is a lack on studies about the reliability of PCB embedded power electronics, especially under humidity stress. This study uses test vehicles with functional diodes embedded into the PCB. The reliability of the test vehicles is studied under HV-H3TRB conditions. A critical leakage current is observed after 200h with a benzoxazine based prepreg and after 600h for an epoxy based prepreg. A rootcause analysis revealed lift-off of the polyimide layer and subsequent electrochemical corrosion as failure mechanism. The delamination is most likely triggered by the Au surface on the chips top metal pad. A second set of test samples was fabricated using an improved surface treatment before lamination. 75% of these samples passed the 1000h H3TRB test successfully.
This paper proposes an asymmetric Single-Chip-Prepackage (SCP) with thick Cu substrate for the optimum electrical and thermal performance of the GaN-HEMT devices. Additionally, the package features a Ni-based integrated thermistor. Laboratory demonstrators have been fabricated using PCB embedding technology. A full electrical characterization of the packaged device indicates full functionality. The temperature coefficient of the integrated temperature sensor is 𝛼 = 0.00541 /𝐾. Thermal characterization of the SCP shows a junction to heatsink thermal resistance Rth,jh = 3.34 K/W, which is 36 % less than the commercial reference device. A silver sinter based assembly process for system integration of SCP is introduced in view of a planar thermal interface. In a 300 kHz 48 V to 24 V buck-converter operation with 60 Arms output current, a 98% efficiency is achieved.