Configurable Fault Tolerant Circuits and System Level Integration for Self-Awareness

  • Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on-line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system.

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Author: Raphael Segabinazzi FerreiraORCiD, Nevin George, Junchao Chen, Michael Hübner, Milos Krstic, Jörg Nolte, Heinrich Theodor Vierhaus
Document Type:Conference proceeding
Year of Completion:2019
Release Date:2020/01/22
Tag:Configurable circuits; Fault tolerant; Operation modes
GND Keyword:Fehlertoleranz; Integrierte Schaltung; Konfiguration <Informatik>
EU-Project number / Contract (GA) number:722325
Fundername:European Union Horizon 2020 Marie Skłodowska-Curie actions
Source:Proceedings of the Work in Progress Session held in connection with SEAA 2019, the 45th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2019, 22nd EUROMICRO Conference on Digital System Design
Series; issue number:SEA-Publications
Institutes:Fakultät 1 MINT - Mathematik, Informatik, Physik, Elektro- und Informationstechnik / FG Verteilte Systeme und Betriebssysteme
Other Notes:SEA-SR-54 (Bestellnummer)
Licence (German):Keine Lizenz vergeben. Es gilt das deutsche Urheberrecht.
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