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Drones can be connected as a swarm to precisely monitor large agricultural areas and manage them more sustainable. They test sensor technology in real environments and solve complex tasks faster. Key aspects include accurate localization, reliable communication, and dynamic flight control. The localization accuracy of RTK-GNSS-enabled system, which includes GPS, GLONASS, GALILEO positioning systems is compared with Ultra-Wideband (UWB) one. The UPWARDS communication hub is presented as a processing and connection point across swarm agents. This controller also incorporates collision avoidance features and testing of evasion strategies.
Today's multi-cores and future many-cores are NUMA architectures with complex cache hierarchies and multiple memory channels. Depending on the topologies of these memory networks we find everything from true data sharing with shared caches to distributed memory architectures which just pretend to be physical shared memory systems. In fact, most many-cores are hybrid systems that exhibit the characteristics of both distributed systems and SMPs. In this paper we argue in favor of middleware platforms for many-cores. We will discuss the needed functionality in contrast to common distributed system middleware and present micro benchmarks on several architectures to substantiate our claims.
Modularity is a widely used quality measure for graph clusterings. Its exact maximization is prohibitively expensive for large graphs. Popular heuristics progressively merge clusters starting from singletons (coarsening), and optionally improve the resulting clustering by moving vertices between clusters (refinement). This paper experimentally compares existing and new heuristics of this type with respect to their effectiveness (achieved modularity) and runtime. For coarsening, it turns out that the most widely used criterion for merging clusters (modularity increase) is outperformed by other simple criteria, and that a recent multi-step algorithm is no improvement over simple single-step coarsening for these criteria. For refinement, a new multi-level algorithm produces significantly better clusterings than conventional single-level algorithms. A comparison with published benchmark results and algorithm implementations shows that combinations of coarsening and multi-level refinement are competitive with the best algorithms in the literature.
On many-core processors, both operating system kernels and bare metal applications need efficient cross-core coordination and communication. Although explicit shared- memory programming and message passing might provide the best performance, they also limit the system’s control over scheduling. In contrast, interrupt-driven cross-core invocations provide universal coordination mechanisms that also enable preemptive operations across cores. This paper surveys cross- core invocation mechanisms and their usability with respect to prevalent coordination scenarios. We integrated some of these mechanisms into a bare-metal environment for the Intel SCC pro- cessor and will discuss implementation aspects of the interrupt- driven invocations. In conclusion, such invocation mechanisms provide an expressive platform for future operating systems kernels and bare-metal applications.
Many-core processors combine fast on-chip communication
with access to large amounts of shared memory. This
makes it possible to exploit the benefits of distributed as well
as shared memory programming models within single parallel
algorithms. While large amounts of data can be shared in the
memory and caches, coordinating the activities of hundreds
of cores relies on cross core communication mechanisms with
ultra low latency for very small messages. In this paper we
discuss two communication protocols for the Intel SCC and
compare them to the MPI implementation of the SCC. Our
micro-benchmark results underline that special purpose protocols
for small messages make much finer levels of parallelism possible
than general purpose message passing systems.
Index Terms—many-core, message passing, shared memory
With the evolution toward fast networks of many-core processors, the design assumptions at the basis of software-level distributed shared memory (DSM) systems change considerably. But efficient DSMs are needed because they can significantly simplify the implementation of complex distributed algorithms. This paper discusses implications of the many-core evolution and derives a set of reusable elementary operations for future software DSMs. These elementary operations will help in exploring and evaluating new memory models and consistency protocols.
Assessing the Feasibility of Combined BLE and Wi-Fi Communication for High Data Sensing Applications
(2023)
Advanced sensors generate more data than can be transmitted using classic battery-powered wireless sensor networks. While using Wi-Fi would provide plenty of throughput, the receivers are energy hungry and, thus, the radio time needs to be reduced. Previous research suggests to combine Wi-Fi with low-power technologies such as BLE for an energy efficient coordination of the Wi-Fi radios. Existing approaches focus on individual point-to-point routes whereas certain applications require concurrent transmissions. We evaluated the combination of BLE and Wi-Fi on the ESP32-S3 multi-radio microcontroller through detailed energy and throughput measurements. The results show that established BLE connections allow to activateWi-Fi quickly on-demand; the energy efficiency of the data transmission is significantly improved over previous works but the BLE connection setup is prohibitively slow. While the combination of BLE and Wi-Fi provides high throughput with good energy efficiency, careful design of the BLE-based signalling protocol is necessary to also achieve low latency.
Many-core architectures trade single-thread performance for a larger number of cores. Scalable throughput can be attained only by a high degree of parallelism, minimized synchronization. Whilst this is achievable for many applications, the operating system still introduces bottlenecks through non-local sharing, synchronization,, message passing. A particular challenge for highly dynamic applications, for example invasive HPC applications, elastic compute clouds, is the management of short-living application threads, processes. This paper discusses OS architecture choices based on microkernel, multikernel, distributed systems designs, our development experience in the context of the MyThOS project. Initial experiments show a much faster thread creation, activation compared to monolithic systems like Linux while providing a more flexible protection, threading model that is better suited for dynamic scenarios. However, despite significant progress in the overall domain of operating systems, the design space for scalable many-core operating systems is yet to be fully explored.
Pseudo-Uniform Memory Architectures hide the memory's throughput bottlenecks and the network's latency differences in order to provide near-peak average throughput for computations on large datasets. This obviates the need for application-level partitioning and load balancing between NUMA domains but the performance of cross-core communication still depends on the actual placement of the involved variables and cores, which can result in significant variation within applications and between application runs.
This paper analyses the pseudo-uniform memory latency on the Intel Xeon Phi Knights Corner processor, derives strategies for the optimised placement of important variables, and discusses the role of localised coordination in pUMA systems. For example, a basic cache line ping-pong benchmark showed a 3x speedup between adjacent cores. Therefore, pUMA systems combined with support for controlled placement of small datasets are an interesting option when processor-wide load balancing is difficult while localised coordination is feasible.
Unmanned Aerial Vehicles (UAVs) are evolving as adaptable platforms for a wide range of applications such as precise inspections, emergency response, and remote sensing.
Autonomous UAV swarms require efficient and stable communication during deployment for a successful mission execution. For instance, the periodic exchange of telemetry data between all swarm members provides the foundation for formation flight and collision avoidance. However, due to the mobility of the vehicles and instability of wireless transmissions, maintaining a secure and reliable all-to-all communication remains challenging.
This paper investigates encrypted and authenticated multi-hop broadcast communication based on the transmission of custom IEEE 802.11 Wi-Fi data frames.
Small Unmanned Aerial Vehicles (UAVs) have vast application potential from industrial logistics and disaster monitoring to smart farming, for example, to create maps with Normalized Difference Vegetation Index (NDVI) cameras and AI-based image classification or the precision spot application of fertilizers. Operating multiple UAVs in parallel, including those with different specializations, enables efficient coverage of large areas. While existing research focused mainly on predefined flight formations for swarms or autonomous missions for single UAVs, the focus of this work is on multiple UAVs with individually adaptable missions. We derive communication system requirements from swarm coordination algorithms and present a respective design. The resulting modular architecture enables future research on autonomous adaptive UAV swarms and their use as flying sensor platforms.
The tiny logic elements in modern integrated circuits increase the rate of transient failures significantly. Therefore, redundancy on various levels is necessary to retain reliability. However, for mixed-criticality scenarios, the typical processor designs offer either too little fault-tolerance or too much redundancy for one part of the applications. Amongst others, we specifically address redundant processor internal functional units (FU) to cope with transient errors and support wear leveling. A real-time operating system (RTOS) was extended to control our prototypical hardware platform and, since it can be configured deterministically within few clock cycles, we are able to reconfigure the FUs dynamically, at process switching time, according to the specified critically of the running processes. Our mechanisms were integrated into the Plasma processor and the Plasma-RTOS. With few changes to the original software code, it was, for example, possible to quickly change from fault-detecting to fault-correcting modes of the processor on demand.
Hardware and software consistency protocols rely on global observability of consistency events. Acknowledged broadcast is an obvious choice to propagate these events. This paper presents a generalized ring topology for parallel event propagation with acknowledged delivery. Implementations for various many-core architectures show increased performance over conventional approaches. Therefore, diamond rings are a prime candidate for implementations of distributed memory models.