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Enabling Communication with FPGA-based Network-attached Accelerators for HPC Workloads

  • The use of stand-alone, network-coupled Field Programmable Gate Array (FPGA) accelerators is intended to significantly increase the energy efficiency of HPC applications and thus also of HPC data centers. A loose coupling between the nodes of the HPC data center and the FPGAs is established through the high-speed network of the data center. This allows greater flexibility in combining different nodes and accelerators. Both the resulting energy savings and the increased flexibility through the network connection, enable the economical use of FPGAs. This work presents a communication stack to integrate the so-called Network-attached Accelerator (NAA) into the HPC data center. A low-level Remote Direct Memory Access (RDMA) Application Programming Interface (API) and a high-level Remote Procedure Call (RPC) API is designed on top of the RDMA over Converged Ethernet v2 (RoCEv2) communication stack. The experimental results over 100 Gbps RoCEv2 show that our design and implementation deliver performance close to the theoretical maximum.
Author:Steffen ChristgauORCiDGND, Dylan EveringhamORCiD, Florian MikolajczakORCiD, Niklas ScheltenORCiD, Bettina SchnorORCiD, Max SchroetterORCiD, Benno StabernackORCiD, Fritjof SteinertORCiD
Document Type:In Proceedings
Parent Title (English):Proceedings of the SC'23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis, SC-W 2023, Denver, CO, USA, November 12-17, 2023
First Page:530
Last Page:538
Year of first publication:2023
Page Number:9
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