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MPI Passive Target Synchronization on a Non-Cache-Coherent Shared-Memory Processor

Please always quote using this URN: urn:nbn:de:0297-zib-74774
  • MPI passive target synchronization offers exclusive and shared locks. These are the building blocks for the implementation of applications with Readers & Writers semantic, like for example distributed hash tables. This paper discusses the implementation of MPI passive target synchronization on a non-cache-coherent multicore, the Intel Single-Chip Cloud Computer. The considered algorithms differ in their communication style (message based versus shared memory), their data structures (centralized versus distributed) and their semantics (with/without Writer preference). It is shown that shared memory approaches scale very well and deliver good performance, even in absence of cache coherence.

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Author:Steffen ChristgauORCiDGND, Bettina Schnor
Document Type:ZIB-Report
Tag:MPI; process synchronization; programming models and systems for manycores
CCS-Classification:C. Computer Systems Organization / C.1 PROCESSOR ARCHITECTURES / C.1.2 Multiple Data Stream Architectures (Multiprocessors) / Multiple-instruction-stream, multiple-data-stream processors (MIMD)
D. Software / D.1 PROGRAMMING TECHNIQUES (E) / D.1.3 Concurrent Programming / Parallel programming
Date of first Publication:2019/10/21
Series (Serial Number):ZIB-Report (19-52)
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