SIMD Enabled Functions on Intel Xeon CPU and Intel Xeon Phi Coprocessor

Please always quote using this URN: urn:nbn:de:0297-zib-54163
  • To achieve high floating point compute performance, modern processors draw on short vector SIMD units, as found e.g. in Intel CPUs (SSE, AVX1, AVX2 as well as AVX-512 on the roadmap) and the Intel Xeon Phi coprocessor, to operate an increasingly larger number of operands simultaneously. Making use of SIMD vector operations therefore is essential to get close to the processor’s floating point peak performance. Two approaches are typically used by programmers to utilize the vector units: compiler driven vectorization via directives and code annotations, and manual vectorization by means of SIMD intrinsic operations or assembly. In this paper, we investigate the capabilities of the current Intel compiler (version 15 and later) to generate vector code for non-trivial coding patterns within loops. Beside the more or less uniform data-parallel standard loops or loop nests, which are typical candidates for SIMDfication, the occurrence of e.g. (conditional) function calls including branching, and early returns from functions may pose difficulties regarding the effective use of vector operations. Recent improvements of the compiler's capabilities involve the generation of SIMD-enabled functions. We will study the effectiveness of the vector code generated by the compiler by comparing it against hand-coded intrinsics versions of different kinds of functions that are invoked within innermost loops.

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Author:Florian Wende
Document Type:ZIB-Report
MSC-Classification:00-XX GENERAL
CCS-Classification:B. Hardware
PACS-Classification:00.00.00 GENERAL
Date of first Publication:2015/03/24
Series (Serial Number):ZIB-Report (15-17)

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