Using FPGA-based Network-Attached Accelerators for Energy-Efficient AI Training in HPC Datacenters
accepted for publication
- FPGA-based Network-Attached Accelerators offer a disaggregated alternative to closely-coupled FPGAs or GPUs, but their adoption is very limited due to missing hardware/software frameworks. However, the usability and energy-efficiency of FPGAs for HPC use-cases has been demonstrated previously. Yet, the support by HPC infrastructure for those devices is lacking behind other accelerators. This paper addresses this shortcoming and demonstrates a full-stack approach that seamlessly integrates Network-Attached Accelerators in HPC datacenters and allows flexible and scalable usage of FPGAs. The presented work includes the according framework, integration steps and a show-case application from the geoscience domain. We evaluate our approach by comparing the training of a Physics-Informed Neural Network on the NAA against two GPU implementations. The NAA reduces total energy consumption by about 50% and 17% compared to the Keras and CUDA implementation, respectively. These results demonstrate that FPGA-based NAAs can be successfully integrated into HPC environments and are a viable path toward more energy-efficient AI training.
| Author: | Niklas ScheltenORCiD, Steffen ChristgauORCiDGND, Merit Hutzler, Philipp KreowskyORCiD, Marco De LuciaORCiD, Bettina SchnorORCiD, Hannes SignerORCiD, Johannes Spazier, Benno StabernackORCiD, Serhii Yahdzhyiev |
|---|---|
| Document Type: | In Proceedings |
| Parent Title (English): | 2026 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) |
| Year of first publication: | 2026 |

