TY - CHAP A1 - Lasby, Mike A1 - Zimmer, Max A1 - Pokutta, Sebastian A1 - Schultheis, Erik T1 - Compressed sparse tiles for memory-efficient unstructured and semi-structured sparsity T2 - Proceedings of the ICLR Workshop on Sparsity in LLMs Y1 - 2025 UR - https://openreview.net/forum?id=iso0KV2HVq ER - TY - CHAP A1 - Fukuda, Takuma A1 - Kera, Hiroshi A1 - Kawamoto, Kazuhiko T1 - Adapter Merging with Centroid Prototype Mapping for Scalable Class-Incremental Learning T2 - 2025 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR) Y1 - 2025 U6 - https://doi.org/10.1109/CVPR52734.2025.00460 SP - 4884 EP - 4893 ER - TY - CHAP A1 - Haase, Jennifer A1 - Hanel, Paul H. P. A1 - Pokutta, Sebastian T1 - S-DAT: a multilingual, GenAI-driven framework for automated divergent thinking assessment T2 - Proceedings of the AAAI/ACM Conference on AI, Ethics, and Society (AIES) Y1 - 2025 VL - 8 SP - 1194 EP - 1205 ER - TY - CHAP A1 - Villim, Ján A1 - Nguyen, Martin A1 - Bobik, Pavol A1 - Genci, Jan A1 - Gecášek, Daniel T1 - New Version of the COR Simulation Engine T2 - Proceedings of 39th International Cosmic Ray Conference — PoS(ICRC2025) N2 - The COR simulation engine is a tool devoted to evaluating cosmic ray trajectories in Earth's magnetosphere. It is part of the COR System, available at https://cor.crmodels.org, and it also functions as a standalone command line tool. The former tool was published in 2022. We report the new version of the tool status with improved performance, precision, new functions/features, and refactored code. Y1 - 2025 U6 - https://doi.org/https://doi.org/10.22323/1.501.1377 VL - 501 PB - Sissa Medialab CY - Trieste, Italy ER - TY - CHAP A1 - Schelten, Niklas A1 - Christgau, Steffen A1 - Schulte, Anton A1 - Schnor, Bettina A1 - Signer, Hannes A1 - Stabernack, Benno T1 - A Flexible Open-Source Framework for FPGA-based Network-Attached Accelerators using SpinalHDL T2 - Architecture of Computing Systems - 39th International Conference, ARCS 2026, Mainz, Germany, March 24-26, 2026, Proceedings. N2 - Domain-specific accelerators are increasingly vital in heterogeneous computing systems, driven by the demand for higher computational capacity and especially energy efficiency. Network-attached FPGAs promise a scalable and flexible alternative to closely coupled FPGAs for integrating accelerators into computing environments. While the advantages of specialized hardware implementations are apparent, traditional hardware development and integration remain time-consuming and complex. We present an open-source framework which combines a hardware shell with supporting software libraries, which enables fast development and deployment of FPGA-based network-attached accelerators. In contrast to traditional approaches using VHDL or Verilog, we leverage generative programming with SpinalHDL, providing a flexible hardware description with multi-level abstractions. This work eases the integration of accelerators into existing network infrastructures and simplifies adaptation to different FPGAs, eliminating complex and lengthy top-level hardware descriptions. Y1 - 2026 ER - TY - CHAP A1 - Gonnermann-Müller, Jana A1 - Sahling, Kristina A1 - Haase, Jennifer T1 - Let's Be Realistic: AI-Recommender Use in a Complex Management Setting T2 - CHI EA '25: Proceedings of the Extended Abstracts of the CHI Conference on Human Factors in Computing Systems Y1 - 2025 U6 - https://doi.org/10.1145/3706599.3720131 ER - TY - CHAP A1 - Schelten, Niklas A1 - Christgau, Steffen A1 - Hutzler, Merit A1 - Kreowsky, Philipp A1 - De Lucia, Marco A1 - Schnor, Bettina A1 - Signer, Hannes A1 - Spazier, Johannes A1 - Stabernack, Benno A1 - Yahdzhyiev, Serhii T1 - Using FPGA-based Network-Attached Accelerators for Energy-Efficient AI Training in HPC Datacenters T2 - 2026 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) N2 - FPGA-based Network-Attached Accelerators offer a disaggregated alternative to closely-coupled FPGAs or GPUs, but their adoption is very limited due to missing hardware/software frameworks. However, the usability and energy-efficiency of FPGAs for HPC use-cases has been demonstrated previously. Yet, the support by HPC infrastructure for those devices is lacking behind other accelerators. This paper addresses this shortcoming and demonstrates a full-stack approach that seamlessly integrates Network-Attached Accelerators in HPC datacenters and allows flexible and scalable usage of FPGAs. The presented work includes the according framework, integration steps and a show-case application from the geoscience domain. We evaluate our approach by comparing the training of a Physics-Informed Neural Network on the NAA against two GPU implementations. The NAA reduces total energy consumption by about 50% and 17% compared to the Keras and CUDA implementation, respectively. These results demonstrate that FPGA-based NAAs can be successfully integrated into HPC environments and are a viable path toward more energy-efficient AI training. Y1 - 2026 ER - TY - CHAP A1 - Sunkara, Vikram A1 - Rostami, Atefe A1 - von Tycowicz, Christoph A1 - Schütte, Christof T1 - Stop throwing away your Decoder; extract the learnt local coordinate system using Latent-XAI T2 - The 4th World Conference on Explainable Artificial Intelligence (XAI-2026) Y1 - 2026 ER -