TY - GEN A1 - Dreßler, Sebastian A1 - Steinke, Thomas T1 - An Automated Approach for Estimating the Memory Footprint of Non-Linear Data Objects N2 - Current programming models for heterogeneous devices with disjoint physical memory spaces require explicit allocation of device memory and explicit data transfers. While it is quite easy to manually implement these operations for linear data objects like arrays, this task becomes more difficult for non-linear objects, e.g. linked lists or multiple inherited classes. The difficulties arise due to dynamic memory requirements at run-time and the dependencies between data structures. In this paper we present a novel method to build a graph-based static data type description which is used to create code for injectable functions that automatically determine the memory footprint of data objects at run-time. Our approach is extensible to implement automatically generated optimized data transfers across physical memory spaces. T3 - ZIB-Report - 13-46 KW - memory footprint KW - non-linear objects KW - static analysis KW - dynamic analysis Y1 - 2013 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:0297-zib-42224 SN - 1438-0064 ER - TY - JOUR A1 - Wende, Florian A1 - Marsman, Martijn A1 - Kim, Jeongnim A1 - Vasilev, Fedor A1 - Zhao, Zhengji A1 - Steinke, Thomas T1 - OpenMP in VASP: Threading and SIMD JF - International Journal of Quantum Chemistry N2 - The Vienna Ab initio Simulation Package (VASP) is a widely used electronic structure code that originally exploits process-level parallelism through the Message Passing Interface (MPI) for work distribution within and across nodes. Architectural changes of modern parallel processors urge programmers to address thread- and data-level parallelism as well to benefit most from the available compute resources within a node. We describe for VASP how to approach for an MPI + OpenMP parallelization including data-level parallelism through OpenMP SIMD constructs together with a generic high-level vector coding scheme. We can demonstrate an improved scalability of VASP and more than 20% gain over the MPI-only version, as well as a 2x increased performance of collective operations using the multiple-endpoint MPI feature. The high-level vector coding scheme applied to VASP's general gradient approximation routine gives up 9x performance gain on AVX512 platforms with the Intel compiler. Y1 - 2018 U6 - https://doi.org/10.1002/qua.25851 IS - Emerging Architectures in Computational Chemistry SP - e25851 PB - Wiley Online Library ER - TY - THES A1 - Deppisch, Daniel T1 - Advancing the Heterogeneous Active Messages Approach Y1 - 2019 ER - TY - GEN A1 - Noack, Matthias A1 - Wende, Florian A1 - Zitzlsberger, Georg A1 - Klemm, Michael A1 - Steinke, Thomas T1 - KART – A Runtime Compilation Library for Improving HPC Application Performance N2 - The effectiveness of ahead-of-time compiler optimization heavily depends on the amount of available information at compile time. Input-specific information that is only available at runtime cannot be used, although it often determines loop counts, branching predicates and paths, as well as memory-access patterns. It can also be crucial for generating efficient SIMD-vectorized code. This is especially relevant for the many-core architectures paving the way to exascale computing, which are more sensitive to code-optimization. We explore the design-space for using input-specific information at compile-time and present KART, a C++ library solution that allows developers to compile, link, and execute code (e.g., C, C++ , Fortran) at application runtime. Besides mere runtime compilation of performance-critical code, KART can be used to instantiate the same code multiple times using different inputs, compilers, and options. Other techniques like auto-tuning and code-generation can be integrated into a KART-enabled application instead of being scripted around it. We evaluate runtimes and compilation costs for different synthetic kernels, and show the effectiveness for two real-world applications, HEOM and a WSM6 proxy. T3 - ZIB-Report - 16-48 Y1 - 2016 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:0297-zib-60730 SN - 1438-0064 ER - TY - CHAP A1 - Krzikalla, Olaf A1 - Wende, Florian A1 - Höhnerbach, Markus T1 - Dynamic SIMD Vector Lane Scheduling T2 - High Performance Computing, ISC High Performance 2016 International Workshops, ExaComm, E-MuCoCoS, HPC-IODC, IXPUG, IWOPH, P^3MA, VHPC, WOPSSS N2 - A classical technique to vectorize code that contains control flow is a control-flow to data-flow conversion. In that approach statements are augmented with masks that denote whether a given vector lane participates in the statement’s execution or idles. If the scheduling of work to vector lanes is performed statically, then some of the vector lanes will run idle in case of control flow divergences or varying work intensities across the loop iterations. With an increasing number of vector lanes, the likelihood of divergences or heavily unbalanced work assignments increases and static scheduling leads to a poor resource utilization. In this paper, we investigate different approaches to dynamic SIMD vector lane scheduling using the Mandelbrot set algorithm as a test case. To overcome the limitations of static scheduling, idle vector lanes are assigned work items dynamically, thereby minimizing per-lane idle cycles. Our evaluation on the Knights Corner and Knights Landing platform shows, that our approaches can lead to considerable performance gains over a static work assignment. By using the AVX-512 vector compress and expand instruction, we are able to further improve the scheduling. Y1 - 2016 U6 - https://doi.org/10.1007/978-3-319-46079-6_25 VL - 9945 SP - 354 EP - 365 ER - TY - CHAP A1 - Wende, Florian A1 - Noack, Matthias A1 - Steinke, Thomas A1 - Klemm, Michael A1 - Zitzlsberger, Georg A1 - Newburn, Chris J. ED - Dutot, Pierre-Francois ED - Trystram, Denis T1 - Portable SIMD Performance with OpenMP* 4.x Compiler Directives N2 - Effective vectorization is becoming increasingly important for high performance and energy efficiency on processors with wide SIMD units. Compilers often require programmers to identify opportunities for vectorization, using directives to disprove data dependences. The OpenMP 4.x SIMD directives strive to provide portability. We investigate the ability of current compilers (GNU, Clang, and Intel) to generate SIMD code for microbenchmarks that cover common patterns in scientific codes and for two kernels from the VASP and the MOM5/ERGOM application. We explore coding strategies for improving SIMD performance across different compilers and platforms (Intel® Xeon® processor and Intel® Xeon Phi™ (co)processor). We compare OpenMP* 4.x SIMD vectorization with and without vector data types against SIMD intrinsics and C++ SIMD types. Our experiments show that in many cases portable performance can be achieved. All microbenchmarks are available as open source as a reference for programmers and compiler experts to enhance SIMD code generation. Y1 - 2016 SN - 978-3-319-43659-3 U6 - https://doi.org/10.1007/978-3-319-43659-3_20 VL - Euro-Par 2016: Parallel Processing: 22nd International Conference on Parallel and Distributed Computing PB - Springer International Publishing ER - TY - CHAP A1 - Wende, Florian A1 - Marsman, Martijn A1 - Steinke, Thomas T1 - On Enhancing 3D-FFT Performance in VASP T2 - CUG Proceedings Y1 - 2016 ER - TY - THES A1 - Kammeyer, Alexander T1 - Evaluierung autovektorisierender Compiler anhand von Schleifenklassen N2 - Modern CPU architectures require the use of vector instructions to fully exploit the available performance. State-of-the art compilers offer means to automatically vectorize program code. In this thesis these compilers are assessed on test cases and their capabilities to auto\-{}vectorize are evaluated to show strengths and weaknesses of the compilers. Run time measurements and vectorizations are compared to another and recommendations depending on the use case are presented. N2 - Moderne CPU-Architekturen erfordern die Verwendung von Vektorinstruktionen, um die vorhandene Leistung vollständig auszuschöpfen. Aktuelle Compiler bieten Möglichkeiten zur automatischen Vektorisierung von Programmcode. Im Rahmen dieser Arbeit werden an Testfällen verschiedene Compiler auf ihre Fähigkeiten zur Autovektorisierung getestet und evaluiert, um Stärken und Schwächen der jeweiligen Compiler aufzuzeigen. Es werden Laufzeitergebnisse und Vektorisierungsvermögen miteinander verglichen und eine Empfehlung in Abhängigkeit des jeweiligen Anwendungsfalls gegeben. Y1 - 2016 ER - TY - CHAP A1 - Noack, Matthias A1 - Reinefeld, Alexander A1 - Kramer, Tobias A1 - Steinke, Thomas T1 - DM-HEOM: A Portable and Scalable Solver-Framework for the Hierarchical Equations of Motion T2 - 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 19th IEEE Int. Workshop on Parallel and Distributed Scientific and Engineering Computing (PDSEC 2018) N2 - Computing the Hierarchical Equations of Motion (HEOM) is by itself a challenging problem, and so is writing portable production code that runs efficiently on a variety of architectures while scaling from PCs to supercomputers. We combined both challenges to push the boundaries of simulating quantum systems, and to evaluate and improve methodologies for scientific software engineering. Our contributions are threefold: We present the first distributed memory implementation of the HEOM method (DM-HEOM), we describe an interdisciplinary development workflow, and we provide guidelines and experiences for designing distributed, performance-portable HPC applications with MPI-3, OpenCL and other state-of-the-art programming models. We evaluated the resulting code on multi- and many-core CPUs as well as GPUs, and demonstrate scalability on a Cray XC40 supercomputer for the PS I molecular light harvesting complex. Y1 - 2018 SN - 978-1-5386-5555-9 U6 - https://doi.org/10.1109/IPDPSW.2018.00149 N1 - Best Paper Award SP - 947 EP - 956 ER - TY - CHAP A1 - Christgau, Steffen A1 - Steinke, Thomas T1 - Porting a Legacy CUDA Stencil Code to oneAPI T2 - 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020, New Orleans, LA, USA, May 18-22, 2020 N2 - Recently, Intel released the oneAPI programming environment. With Data Parallel C++ (DPC++), oneAPI enables codes to target multiple hardware architectures like multi-core CPUs, GPUs, and even FPGAs or other hardware using a single source. For legacy codes that were written for Nvidia GPUs, a compatibility tool is provided which facilitates the transition to the SYCL-based DPC++ programming language. This paper presents early experiences when using both the compatibility tool and oneAPI as well the employed extension to the SYCL programming standard for the tsunami simulation code easyWave. A performance study compares the original code running on Xeon processors using OpenMP as well as CUDA with the performance of the DPC++ counter part on multicore CPUs as well as integrated GPUs. Y1 - 2020 SN - 978-1-7281-7445-7 U6 - https://doi.org/10.1109/IPDPSW50202.2020.00070 SP - 359 EP - 367 PB - IEEE CY - New Orleans ER -