TY - GEN A1 - Christgau, Steffen A1 - Schnor, Bettina T1 - MPI Passive Target Synchronization on a Non-Cache-Coherent Shared-Memory Processor N2 - MPI passive target synchronization offers exclusive and shared locks. These are the building blocks for the implementation of applications with Readers & Writers semantic, like for example distributed hash tables. This paper discusses the implementation of MPI passive target synchronization on a non-cache-coherent multicore, the Intel Single-Chip Cloud Computer. The considered algorithms differ in their communication style (message based versus shared memory), their data structures (centralized versus distributed) and their semantics (with/without Writer preference). It is shown that shared memory approaches scale very well and deliver good performance, even in absence of cache coherence. T3 - ZIB-Report - 19-52 KW - process synchronization KW - programming models and systems for manycores KW - MPI Y1 - 2019 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:0297-zib-74774 SN - 1438-0064 ER -