TY - CHAP A1 - Steinke, Thomas A1 - Reinefeld, Alexander T1 - Experiences with High-Level Programming of FPGAs on Cray XD1 T2 - CUG Proceedings Y1 - 2006 ER - TY - CHAP A1 - May, Patrick A1 - Klau, Gunnar A1 - Bauer, Markus A1 - Steinke, Thomas ED - Dubitzky, W. T1 - Accelerated microRNA-Precursor Detection Using the Smith-Waterman Algorithm on FPGAs T2 - GCCB Y1 - 2007 VL - 4360 SP - 19 EP - 32 PB - Springer ER - TY - JOUR A1 - Meyer, Michael A1 - Steinke, Thomas A1 - Sühnel, Jürgen T1 - Density functional study of isoguanine tetrad and pentad sandwich complexes with alkali metal ions JF - Journal of Molecular Modeling Y1 - 2007 UR - http://dx.doi.org/10.1007/s00894-006-0148-5 VL - 13 IS - 2 SP - 335 EP - 345 PB - Springer Berlin / Heidelberg ER - TY - CHAP A1 - Schmidtke, Robert A1 - Laubender, Guido A1 - Steinke, Thomas T1 - Big Data Analytics on Cray XC Series DataWarp using Hadoop, Spark and Flink T2 - CUG Proceedings Y1 - 2016 ER - TY - JOUR A1 - Cordes, Frank A1 - Preissner, Robert A1 - Steinke, Thomas T1 - How Does a Protein Work? JF - BioTOPics J. of Biotechnology Berlin-Brandenburg Y1 - 2003 VL - 18 IS - 2 SP - 4 EP - 5 ER - TY - JOUR A1 - Ziegler, Alexander A1 - Ogurreck, Malte A1 - Steinke, Thomas A1 - Beckmann, Felix A1 - Prohaska, Steffen A1 - Ziegler, Andreas T1 - Opportunities and challenges for digital morphology JF - Biology Direct Y1 - 2010 U6 - https://doi.org/10.1186/1745-6150-5-45 VL - 5 IS - 1 SP - 45 ER - TY - JOUR A1 - Grunzke, Richard A1 - Breuers, Sebastian A1 - Gesing, Sandra A1 - Herres-Pawlis, Sonja A1 - Kruse, Martin A1 - Blunk, Dirk A1 - de la Garza, Luis A1 - Packschies, Lars A1 - Schäfer, Patrick A1 - Schärfe, Charlotta A1 - Schlemmer, Tobias A1 - Steinke, Thomas A1 - Schuller, Bernd A1 - Müller-Pfefferkorn, Ralph A1 - Jäkel, René A1 - Nagel, Wolfgang A1 - Atkinson, Malcolm A1 - Krüger, Jens T1 - Standards-based metadata management for molecular simulations JF - Concurrency and Computation: Practice and Experience Y1 - 2013 U6 - https://doi.org/10.1002/cpe.3116 ER - TY - CHAP A1 - Baumann, Wolfgang A1 - Laubender, Guido A1 - Läuter, Matthias A1 - Reinefeld, Alexander A1 - Schimmel, Christian A1 - Steinke, Thomas A1 - Tuma, Christian A1 - Wollny, Stefan ED - Vetter, Jeffrey S. T1 - HLRN-III at Zuse Institute Berlin T2 - Contemporary High Performance Computing: From Petascale toward Exascale, Volume Two Y1 - 2015 UR - http://www.crcpress.com/product/isbn/9781498700627 SN - 9781498700627 SP - 81 EP - 114 PB - Chapman and Hall/CRC ER - TY - CHAP A1 - Noack, Matthias A1 - Focht, Erich A1 - Steinke, Thomas T1 - Heterogeneous Active Messages for Offloading on the NEC SX-Aurora TSUBASA T2 - 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Heterogeneity in Computing Workshop (HCW 2019) N2 - The NEC SX-Aurora TSUBASA is a new generation of vector processing architectures that combines a standard Intel Xeon host with the newly developed NEC Vector Engine co-processor cards. One way to use these co-processors is offloading suitable parts of the program from the host to the Vector Engines. Currently, the only vendor-provided offloading solutions are the low-level Vector Engine Offloading (VEO) library, and a builtin reverse-offloading mechanism named VHcall. In this work, we extend the portable Heterogeneous Active Messages (HAM) based HAM-Offload framework with support for the NEC SX-Aurora TSUBASA. Therefore, we design, implement, and evaluate two messaging protocols aimed at minimising offloading cost. This sheds some light on how to achieve fast communication between host CPU and the Vector Engines of the NEC SX-Aurora TSUBASA. Compared with VEO, the DMA-based protocol reduces offloading overhead by a factor of 13×. The resulting framework enables users to write portable offload applications with low overhead, that do neither require a language extension like OpenMP, nor a special language like OpenCL. Existing HAM-Offload applications are now ready to run on the NEC SX-Aurora TSUBASA. Y1 - 2019 ER - TY - CHAP A1 - Christgau, Steffen A1 - Steinke, Thomas T1 - Porting a Legacy CUDA Stencil Code to oneAPI T2 - 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020, New Orleans, LA, USA, May 18-22, 2020 N2 - Recently, Intel released the oneAPI programming environment. With Data Parallel C++ (DPC++), oneAPI enables codes to target multiple hardware architectures like multi-core CPUs, GPUs, and even FPGAs or other hardware using a single source. For legacy codes that were written for Nvidia GPUs, a compatibility tool is provided which facilitates the transition to the SYCL-based DPC++ programming language. This paper presents early experiences when using both the compatibility tool and oneAPI as well the employed extension to the SYCL programming standard for the tsunami simulation code easyWave. A performance study compares the original code running on Xeon processors using OpenMP as well as CUDA with the performance of the DPC++ counter part on multicore CPUs as well as integrated GPUs. Y1 - 2020 SN - 978-1-7281-7445-7 U6 - https://doi.org/10.1109/IPDPSW50202.2020.00070 SP - 359 EP - 367 PB - IEEE CY - New Orleans ER - TY - CHAP A1 - Christgau, Steffen A1 - Steinke, Thomas T1 - Leveraging a Heterogeneous Memory System for a Legacy Fortran Code: The Interplay of Storage Class Memory, DRAM and OS T2 - 2020 IEEE/ACM Workshop on Memory Centric High Performance Computing (MCHPC) N2 - Large capacity Storage Class Memory (SCM) opens new possibilities for workloads requiring a large memory footprint. We examine optimization strategies for a legacy Fortran application on systems with an heterogeneous memory configuration comprising SCM and DRAM. We present a performance study for the multigrid solver component of the large-eddy simulation framework PALM for different memory configurations with large capacity SCM. An important optimization approach is the explicit assignment of storage locations depending on the data access characteristic to take advantage of the heterogeneous memory configuration. We are able to demonstrate that an explicit control over memory locations provides better performance compared to transparent hardware settings. As on aforementioned systems the page management by the OS appears as critical performance factor, we study the impact of different huge page settings. Y1 - 2020 SN - 978-0-7381-1067-7 U6 - https://doi.org/10.1109/MCHPC51950.2020.00008 SP - 17 EP - 24 PB - IEEE ER - TY - CHAP A1 - Noack, Matthias A1 - Reinefeld, Alexander A1 - Kramer, Tobias A1 - Steinke, Thomas T1 - DM-HEOM: A Portable and Scalable Solver-Framework for the Hierarchical Equations of Motion T2 - 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 19th IEEE Int. Workshop on Parallel and Distributed Scientific and Engineering Computing (PDSEC 2018) N2 - Computing the Hierarchical Equations of Motion (HEOM) is by itself a challenging problem, and so is writing portable production code that runs efficiently on a variety of architectures while scaling from PCs to supercomputers. We combined both challenges to push the boundaries of simulating quantum systems, and to evaluate and improve methodologies for scientific software engineering. Our contributions are threefold: We present the first distributed memory implementation of the HEOM method (DM-HEOM), we describe an interdisciplinary development workflow, and we provide guidelines and experiences for designing distributed, performance-portable HPC applications with MPI-3, OpenCL and other state-of-the-art programming models. We evaluated the resulting code on multi- and many-core CPUs as well as GPUs, and demonstrate scalability on a Cray XC40 supercomputer for the PS I molecular light harvesting complex. Y1 - 2018 SN - 978-1-5386-5555-9 U6 - https://doi.org/10.1109/IPDPSW.2018.00149 N1 - Best Paper Award SP - 947 EP - 956 ER - TY - CHAP A1 - Baumann, Tobias A1 - Noack, Matthias A1 - Steinke, Thomas T1 - Performance Evaluation and Improvements of the PoCL Open-Source OpenCL Implementation on Intel CPUs T2 - IWOCL'21: International Workshop on OpenCL N2 - The Portable Computing Language (PoCL) is a vendor independent open-source OpenCL implementation that aims to support a variety of compute devices in a single platform. Evaluating PoCL versus the Intel OpenCL implementation reveals significant performance drawbacks of PoCL on Intel CPUs – which run 92 % of the TOP500 list. Using a selection of benchmarks, we identify and analyse performance issues in PoCL with a focus on scheduling and vectorisation. We propose a new CPU device-driver based on Intel Threading Building Blocks (TBB), and evaluate LLVM with respect to automatic compiler vectorisation across work-items in PoCL. Using the TBB driver, it is possible to narrow the gap to Intel OpenCL and even outperform it by a factor of up to 1.3× in our proxy application benchmark with a manual vectorisation strategy. Y1 - 2021 U6 - https://doi.org/10.1145/3456669.3456698 ER - TY - JOUR A1 - Alhaddad, Samer A1 - Förstner, Jens A1 - Groth, Stefan A1 - Grünewald, Daniel A1 - Grynko, Yevgen A1 - Hannig, Frank A1 - Kenter, Tobias A1 - Pfreundt, F.J. A1 - Plessl, Christian A1 - Schotte, Merlind A1 - Steinke, Thomas A1 - Teich, J. A1 - Weiser, Martin A1 - Wende, Florian T1 - The HighPerMeshes Framework for Numerical Algorithms on Unstructured Grids JF - Concurrency and Computation: Practice and Experience N2 - Solving PDEs on unstructured grids is a cornerstone of engineering and scientific computing. Heterogeneous parallel platforms, including CPUs, GPUs, and FPGAs, enable energy-efficient and computationally demanding simulations. In this article, we introduce the HPM C++-embedded DSL that bridges the abstraction gap between the mathematical formulation of mesh-based algorithms for PDE problems on the one hand and an increasing number of heterogeneous platforms with their different programming models on the other hand. Thus, the HPM DSL aims at higher productivity in the code development process for multiple target platforms. We introduce the concepts as well as the basic structure of the HPM DSL, and demonstrate its usage with three examples. The mapping of the abstract algorithmic description onto parallel hardware, including distributed memory compute clusters, is presented. A code generator and a matching back end allow the acceleration of HPM code with GPUs. Finally, the achievable performance and scalability are demonstrated for different example problems. Y1 - 2022 U6 - https://doi.org/10.1002/cpe.6616 VL - 34 IS - 14 ER - TY - GEN A1 - Noack, Matthias A1 - Wende, Florian A1 - Zitzlsberger, Georg A1 - Klemm, Michael A1 - Steinke, Thomas T1 - KART – A Runtime Compilation Library for Improving HPC Application Performance N2 - The effectiveness of ahead-of-time compiler optimization heavily depends on the amount of available information at compile time. Input-specific information that is only available at runtime cannot be used, although it often determines loop counts, branching predicates and paths, as well as memory-access patterns. It can also be crucial for generating efficient SIMD-vectorized code. This is especially relevant for the many-core architectures paving the way to exascale computing, which are more sensitive to code-optimization. We explore the design-space for using input-specific information at compile-time and present KART, a C++ library solution that allows developers to compile, link, and execute code (e.g., C, C++ , Fortran) at application runtime. Besides mere runtime compilation of performance-critical code, KART can be used to instantiate the same code multiple times using different inputs, compilers, and options. Other techniques like auto-tuning and code-generation can be integrated into a KART-enabled application instead of being scripted around it. We evaluate runtimes and compilation costs for different synthetic kernels, and show the effectiveness for two real-world applications, HEOM and a WSM6 proxy. T3 - ZIB-Report - 16-48 Y1 - 2016 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:0297-zib-60730 SN - 1438-0064 ER - TY - CHAP A1 - Noack, Matthias A1 - Wende, Florian A1 - Steinke, Thomas A1 - Cordes, Frank T1 - A Unified Programming Model for Intra- and Inter-Node Offloading on Xeon Phi Clusters T2 - SC '14: Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis. SC14, November 16-21, 2014, New Orleans, Louisiana, USA N2 - Standard offload programming models for the Xeon Phi, e.g. Intel LEO and OpenMP 4.0, are restricted to a single compute node and hence a limited number of coprocessors. Scaling applications across a Xeon Phi cluster/supercomputer thus requires hybrid programming approaches, usually MPI+X. In this work, we present a framework based on heterogeneous active messages (HAM-Offload) that provides the means to offload work to local and remote (co)processors using a unified offload API. Since HAM-Offload provides similar primitives as current local offload frameworks, existing applications can be easily ported to overcome the single-node limitation while keeping the convenient offload programming model. We demonstrate the effectiveness of the framework by using it to enable a real-world application from the field of molecular dynamics to use multiple local and remote Xeon Phis. The evaluation shows good scaling behavior. Compared with LEO, performance is equal for large offloads and significantly better for small offloads. Y1 - 2014 UR - http://dl.acm.org/citation.cfm?id=2683616 U6 - https://doi.org/10.1109/SC.2014.22 ER - TY - CHAP A1 - Wende, Florian A1 - Steinke, Thomas A1 - Reinefeld, Alexander ED - Gray, A. ED - Smith, L. ED - Weiland, M. T1 - The Impact of Process Placement and Oversubscription on Application Performance: A Case Study for Exascale Computing T2 - Proceedings of the 3rd International Conference on Exascale Applications and Software, EASC 2015 Y1 - 2015 SN - 978 -0-9 926615 -1-9 SP - 13 EP - 18 PB - The University of Edinburgh ER - TY - CHAP A1 - Wende, Florian A1 - Cordes, Frank A1 - Steinke, Thomas T1 - Concurrent Kernel Execution on Xeon Phi within Parallel Heterogeneous Workloads T2 - Euro-Par 2014: Parallel Processing. 20th International Conference, Porto, Portugal, August 25-29, 2014, Proceedings Y1 - 2014 UR - http://www.springer.com/computer/swe/book/978-3-319-09872-2 U6 - https://doi.org/10.1007/978-3-319-09873-9_66 VL - 8632 SP - 788 EP - 799 ER - TY - CHAP A1 - Wende, Florian A1 - Steinke, Thomas T1 - Swendsen-Wang Multi-Cluster Algorithm for the 2D/3D Ising Model on Xeon Phi and GPU T2 - Proceeding SC '13 Proceedings of SC13: International Conference for High Performance Computing, Networking, Storage and Analysis Article No. 83 ACM New York, NY, USA, 2013 Y1 - 2013 U6 - https://doi.org/http://dx.doi.org/10.1145/2503210.2503254 ER - TY - CHAP A1 - Wende, Florian A1 - Laubender, Guido A1 - Steinke, Thomas T1 - Integration of Intel Xeon Phi Servers into the HLRN-III Complex: Experiences, Performance and Lessons Learned T2 - CUG2014 Proceedings Y1 - 2014 ER -