TY - CHAP A1 - Steinke, Thomas A1 - Reinefeld, Alexander T1 - Experiences with High-Level Programming of FPGAs on Cray XD1 T2 - CUG Proceedings Y1 - 2006 ER - TY - CHAP A1 - May, Patrick A1 - Klau, Gunnar A1 - Bauer, Markus A1 - Steinke, Thomas ED - Dubitzky, W. T1 - Accelerated microRNA-Precursor Detection Using the Smith-Waterman Algorithm on FPGAs T2 - GCCB Y1 - 2007 VL - 4360 SP - 19 EP - 32 PB - Springer ER - TY - JOUR A1 - Meyer, Michael A1 - Steinke, Thomas A1 - Sühnel, Jürgen T1 - Density functional study of isoguanine tetrad and pentad sandwich complexes with alkali metal ions JF - Journal of Molecular Modeling Y1 - 2007 UR - http://dx.doi.org/10.1007/s00894-006-0148-5 VL - 13 IS - 2 SP - 335 EP - 345 PB - Springer Berlin / Heidelberg ER - TY - CHAP A1 - Schmidtke, Robert A1 - Laubender, Guido A1 - Steinke, Thomas T1 - Big Data Analytics on Cray XC Series DataWarp using Hadoop, Spark and Flink T2 - CUG Proceedings Y1 - 2016 ER - TY - JOUR A1 - Cordes, Frank A1 - Preissner, Robert A1 - Steinke, Thomas T1 - How Does a Protein Work? JF - BioTOPics J. of Biotechnology Berlin-Brandenburg Y1 - 2003 VL - 18 IS - 2 SP - 4 EP - 5 ER - TY - JOUR A1 - Ziegler, Alexander A1 - Ogurreck, Malte A1 - Steinke, Thomas A1 - Beckmann, Felix A1 - Prohaska, Steffen A1 - Ziegler, Andreas T1 - Opportunities and challenges for digital morphology JF - Biology Direct Y1 - 2010 U6 - https://doi.org/10.1186/1745-6150-5-45 VL - 5 IS - 1 SP - 45 ER - TY - JOUR A1 - Grunzke, Richard A1 - Breuers, Sebastian A1 - Gesing, Sandra A1 - Herres-Pawlis, Sonja A1 - Kruse, Martin A1 - Blunk, Dirk A1 - de la Garza, Luis A1 - Packschies, Lars A1 - Schäfer, Patrick A1 - Schärfe, Charlotta A1 - Schlemmer, Tobias A1 - Steinke, Thomas A1 - Schuller, Bernd A1 - Müller-Pfefferkorn, Ralph A1 - Jäkel, René A1 - Nagel, Wolfgang A1 - Atkinson, Malcolm A1 - Krüger, Jens T1 - Standards-based metadata management for molecular simulations JF - Concurrency and Computation: Practice and Experience Y1 - 2013 U6 - https://doi.org/10.1002/cpe.3116 ER - TY - CHAP A1 - Baumann, Wolfgang A1 - Laubender, Guido A1 - Läuter, Matthias A1 - Reinefeld, Alexander A1 - Schimmel, Christian A1 - Steinke, Thomas A1 - Tuma, Christian A1 - Wollny, Stefan ED - Vetter, Jeffrey S. T1 - HLRN-III at Zuse Institute Berlin T2 - Contemporary High Performance Computing: From Petascale toward Exascale, Volume Two Y1 - 2015 UR - http://www.crcpress.com/product/isbn/9781498700627 SN - 9781498700627 SP - 81 EP - 114 PB - Chapman and Hall/CRC ER - TY - CHAP A1 - Noack, Matthias A1 - Focht, Erich A1 - Steinke, Thomas T1 - Heterogeneous Active Messages for Offloading on the NEC SX-Aurora TSUBASA T2 - 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Heterogeneity in Computing Workshop (HCW 2019) N2 - The NEC SX-Aurora TSUBASA is a new generation of vector processing architectures that combines a standard Intel Xeon host with the newly developed NEC Vector Engine co-processor cards. One way to use these co-processors is offloading suitable parts of the program from the host to the Vector Engines. Currently, the only vendor-provided offloading solutions are the low-level Vector Engine Offloading (VEO) library, and a builtin reverse-offloading mechanism named VHcall. In this work, we extend the portable Heterogeneous Active Messages (HAM) based HAM-Offload framework with support for the NEC SX-Aurora TSUBASA. Therefore, we design, implement, and evaluate two messaging protocols aimed at minimising offloading cost. This sheds some light on how to achieve fast communication between host CPU and the Vector Engines of the NEC SX-Aurora TSUBASA. Compared with VEO, the DMA-based protocol reduces offloading overhead by a factor of 13×. The resulting framework enables users to write portable offload applications with low overhead, that do neither require a language extension like OpenMP, nor a special language like OpenCL. Existing HAM-Offload applications are now ready to run on the NEC SX-Aurora TSUBASA. Y1 - 2019 ER - TY - CHAP A1 - Christgau, Steffen A1 - Steinke, Thomas T1 - Porting a Legacy CUDA Stencil Code to oneAPI T2 - 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020, New Orleans, LA, USA, May 18-22, 2020 N2 - Recently, Intel released the oneAPI programming environment. With Data Parallel C++ (DPC++), oneAPI enables codes to target multiple hardware architectures like multi-core CPUs, GPUs, and even FPGAs or other hardware using a single source. For legacy codes that were written for Nvidia GPUs, a compatibility tool is provided which facilitates the transition to the SYCL-based DPC++ programming language. This paper presents early experiences when using both the compatibility tool and oneAPI as well the employed extension to the SYCL programming standard for the tsunami simulation code easyWave. A performance study compares the original code running on Xeon processors using OpenMP as well as CUDA with the performance of the DPC++ counter part on multicore CPUs as well as integrated GPUs. Y1 - 2020 SN - 978-1-7281-7445-7 U6 - https://doi.org/10.1109/IPDPSW50202.2020.00070 SP - 359 EP - 367 PB - IEEE CY - New Orleans ER -