TY - GEN A1 - Christgau, Steffen A1 - Schnor, Bettina T1 - MPI Passive Target Synchronization on a Non-Cache-Coherent Shared-Memory Processor N2 - MPI passive target synchronization offers exclusive and shared locks. These are the building blocks for the implementation of applications with Readers & Writers semantic, like for example distributed hash tables. This paper discusses the implementation of MPI passive target synchronization on a non-cache-coherent multicore, the Intel Single-Chip Cloud Computer. The considered algorithms differ in their communication style (message based versus shared memory), their data structures (centralized versus distributed) and their semantics (with/without Writer preference). It is shown that shared memory approaches scale very well and deliver good performance, even in absence of cache coherence. T3 - ZIB-Report - 19-52 KW - process synchronization KW - programming models and systems for manycores KW - MPI Y1 - 2019 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:0297-zib-74774 SN - 1438-0064 ER - TY - JOUR A1 - Christgau, Steffen A1 - Schnor, Bettina T1 - Comparing MPI Passive Target Synchronization on a Non-Cache-Coherent Shared-Memory Processor JF - Mitteilungen - Gesellschaft für Informatik e. V., Parallel-Algorithmen und Rechnerstrukturen, ISSN 0177-0454, 28. PARS-Workshop Y1 - 2020 IS - 35 SP - 121 EP - 132 ER - TY - CHAP A1 - Christgau, Steffen A1 - Everingham, Dylan A1 - Mikolajczak, Florian A1 - Schelten, Niklas A1 - Schnor, Bettina A1 - Schroetter, Max A1 - Stabernack, Benno A1 - Steinert, Fritjof T1 - Enabling Communication with FPGA-based Network-attached Accelerators for HPC Workloads T2 - Proceedings of the SC'23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis, SC-W 2023, Denver, CO, USA, November 12-17, 2023 N2 - The use of stand-alone, network-coupled Field Programmable Gate Array (FPGA) accelerators is intended to significantly increase the energy efficiency of HPC applications and thus also of HPC data centers. A loose coupling between the nodes of the HPC data center and the FPGAs is established through the high-speed network of the data center. This allows greater flexibility in combining different nodes and accelerators. Both the resulting energy savings and the increased flexibility through the network connection, enable the economical use of FPGAs. This work presents a communication stack to integrate the so-called Network-attached Accelerator (NAA) into the HPC data center. A low-level Remote Direct Memory Access (RDMA) Application Programming Interface (API) and a high-level Remote Procedure Call (RPC) API is designed on top of the RDMA over Converged Ethernet v2 (RoCEv2) communication stack. The experimental results over 100 Gbps RoCEv2 show that our design and implementation deliver performance close to the theoretical maximum. Y1 - 2023 U6 - https://doi.org/10.1145/3624062.3624540 SP - 530 EP - 538 PB - ACM ER - TY - CHAP A1 - Christgau, Steffen A1 - Dylan, Everingham A1 - Lübke, Max A1 - De Lucia, Marco A1 - Puhan, Danny A1 - Schelten, Niklas A1 - Schnor, Bettina A1 - Signer, Hannes A1 - Spazier, Johannes A1 - Stabernack, Benno A1 - Steinert, Fritjof A1 - Yahdzhyiev, Serhii T1 - On the Usability and Energy Efficiency of High-Level Synthesis for FPGA-based Network-Attached Accelerators T2 - 2025 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) N2 - Heterogeneity in high performance computing systems is one of the most promising approaches towards more energy-efficient computing on one hand and satisfying the raising demand of global computation capacity on the other hand. Besides the well-known key components like CPUs and GPGPUs are domain-specific accelerators like TPUs, FPGAs well known for their energy efficiency. This is especially true for highly specialized use cases. Network-attached accelerators promise more scalability and flexibility for FPGA usage in HPC environments. Easy and efficient programming of those accelerators is, however, still an open issue. Based on a framework for such accelerators which enables decoupling of FPGAs from their host system, we present a workflow using High-Level Synthesis (HLS) to offload application kernels to them. We evaluate this approach against a conventional Hardware Description Language (HDL) based workflow. In addition, we introduce the energy measurement tool EMA and assess the energy efficiency of both HLS and HDL design. Y1 - 2025 U6 - https://doi.org/10.1109/IPDPSW66978.2025.00139 SP - 886 EP - 895 ER - TY - CHAP A1 - Schelten, Niklas A1 - Christgau, Steffen A1 - Schulte, Anton A1 - Schnor, Bettina A1 - Signer, Hannes A1 - Stabernack, Benno T1 - A Flexible Open-Source Framework for FPGA-based Network-Attached Accelerators using SpinalHDL T2 - Architecture of Computing Systems - 39th International Conference, ARCS 2026, Mainz, Germany, March 24-26, 2026, Proceedings. N2 - Domain-specific accelerators are increasingly vital in heterogeneous computing systems, driven by the demand for higher computational capacity and especially energy efficiency. Network-attached FPGAs promise a scalable and flexible alternative to closely coupled FPGAs for integrating accelerators into computing environments. While the advantages of specialized hardware implementations are apparent, traditional hardware development and integration remain time-consuming and complex. We present an open-source framework which combines a hardware shell with supporting software libraries, which enables fast development and deployment of FPGA-based network-attached accelerators. In contrast to traditional approaches using VHDL or Verilog, we leverage generative programming with SpinalHDL, providing a flexible hardware description with multi-level abstractions. This work eases the integration of accelerators into existing network infrastructures and simplifies adaptation to different FPGAs, eliminating complex and lengthy top-level hardware descriptions. Y1 - 2026 ER - TY - CHAP A1 - Schelten, Niklas A1 - Christgau, Steffen A1 - Hutzler, Merit A1 - Kreowsky, Philipp A1 - De Lucia, Marco A1 - Schnor, Bettina A1 - Signer, Hannes A1 - Spazier, Johannes A1 - Stabernack, Benno A1 - Yahdzhyiev, Serhii T1 - Using FPGA-based Network-Attached Accelerators for Energy-Efficient AI Training in HPC Datacenters T2 - 2026 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) N2 - FPGA-based Network-Attached Accelerators offer a disaggregated alternative to closely-coupled FPGAs or GPUs, but their adoption is very limited due to missing hardware/software frameworks. However, the usability and energy-efficiency of FPGAs for HPC use-cases has been demonstrated previously. Yet, the support by HPC infrastructure for those devices is lacking behind other accelerators. This paper addresses this shortcoming and demonstrates a full-stack approach that seamlessly integrates Network-Attached Accelerators in HPC datacenters and allows flexible and scalable usage of FPGAs. The presented work includes the according framework, integration steps and a show-case application from the geoscience domain. We evaluate our approach by comparing the training of a Physics-Informed Neural Network on the NAA against two GPU implementations. The NAA reduces total energy consumption by about 50% and 17% compared to the Keras and CUDA implementation, respectively. These results demonstrate that FPGA-based NAAs can be successfully integrated into HPC environments and are a viable path toward more energy-efficient AI training. Y1 - 2026 ER -