TY - CHAP A1 - Christgau, Steffen A1 - Dylan, Everingham A1 - Lübke, Max A1 - De Lucia, Marco A1 - Puhan, Danny A1 - Schelten, Niklas A1 - Schnor, Bettina A1 - Signer, Hannes A1 - Spazier, Johannes A1 - Stabernack, Benno A1 - Steinert, Fritjof A1 - Yahdzhyiev, Serhii T1 - On the Usability and Energy Efficiency of High-Level Synthesis for FPGA-based Network-Attached Accelerators T2 - 2025 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) N2 - Heterogeneity in high performance computing systems is one of the most promising approaches towards more energy-efficient computing on one hand and satisfying the raising demand of global computation capacity on the other hand. Besides the well-known key components like CPUs and GPGPUs are domain-specific accelerators like TPUs, FPGAs well known for their energy efficiency. This is especially true for highly specialized use cases. Network-attached accelerators promise more scalability and flexibility for FPGA usage in HPC environments. Easy and efficient programming of those accelerators is, however, still an open issue. Based on a framework for such accelerators which enables decoupling of FPGAs from their host system, we present a workflow using High-Level Synthesis (HLS) to offload application kernels to them. We evaluate this approach against a conventional Hardware Description Language (HDL) based workflow. In addition, we introduce the energy measurement tool EMA and assess the energy efficiency of both HLS and HDL design. Y1 - 2025 U6 - https://doi.org/10.1109/IPDPSW66978.2025.00139 SP - 886 EP - 895 ER - TY - CHAP A1 - Schelten, Niklas A1 - Christgau, Steffen A1 - Hutzler, Merit A1 - Kreowsky, Philipp A1 - De Lucia, Marco A1 - Schnor, Bettina A1 - Signer, Hannes A1 - Spazier, Johannes A1 - Stabernack, Benno A1 - Yahdzhyiev, Serhii T1 - Using FPGA-based Network-Attached Accelerators for Energy-Efficient AI Training in HPC Datacenters T2 - 2026 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) N2 - FPGA-based Network-Attached Accelerators offer a disaggregated alternative to closely-coupled FPGAs or GPUs, but their adoption is very limited due to missing hardware/software frameworks. However, the usability and energy-efficiency of FPGAs for HPC use-cases has been demonstrated previously. Yet, the support by HPC infrastructure for those devices is lacking behind other accelerators. This paper addresses this shortcoming and demonstrates a full-stack approach that seamlessly integrates Network-Attached Accelerators in HPC datacenters and allows flexible and scalable usage of FPGAs. The presented work includes the according framework, integration steps and a show-case application from the geoscience domain. We evaluate our approach by comparing the training of a Physics-Informed Neural Network on the NAA against two GPU implementations. The NAA reduces total energy consumption by about 50% and 17% compared to the Keras and CUDA implementation, respectively. These results demonstrate that FPGA-based NAAs can be successfully integrated into HPC environments and are a viable path toward more energy-efficient AI training. Y1 - 2026 ER -