TY - JOUR A1 - Alhaddad, Samer A1 - Förstner, Jens A1 - Groth, Stefan A1 - Grünewald, Daniel A1 - Grynko, Yevgen A1 - Hannig, Frank A1 - Kenter, Tobias A1 - Pfreundt, F.J. A1 - Plessl, Christian A1 - Schotte, Merlind A1 - Steinke, Thomas A1 - Teich, J. A1 - Weiser, Martin A1 - Wende, Florian T1 - The HighPerMeshes Framework for Numerical Algorithms on Unstructured Grids JF - Concurrency and Computation: Practice and Experience N2 - Solving PDEs on unstructured grids is a cornerstone of engineering and scientific computing. Heterogeneous parallel platforms, including CPUs, GPUs, and FPGAs, enable energy-efficient and computationally demanding simulations. In this article, we introduce the HPM C++-embedded DSL that bridges the abstraction gap between the mathematical formulation of mesh-based algorithms for PDE problems on the one hand and an increasing number of heterogeneous platforms with their different programming models on the other hand. Thus, the HPM DSL aims at higher productivity in the code development process for multiple target platforms. We introduce the concepts as well as the basic structure of the HPM DSL, and demonstrate its usage with three examples. The mapping of the abstract algorithmic description onto parallel hardware, including distributed memory compute clusters, is presented. A code generator and a matching back end allow the acceleration of HPM code with GPUs. Finally, the achievable performance and scalability are demonstrated for different example problems. Y1 - 2022 U6 - https://doi.org/10.1002/cpe.6616 VL - 34 IS - 14 ER - TY - JOUR A1 - Alhaddad, Samer A1 - Förstner, Jens A1 - Groth, Stefan A1 - Grünewald, Daniel A1 - Grynko, Yevgen A1 - Hannig, Frank A1 - Kenter, Tobias A1 - Pfreundt, Franz-Josef A1 - Plessl, Christian A1 - Schotte, Merlind A1 - Steinke, Thomas A1 - Teich, Jürgen A1 - Weiser, Martin A1 - Wende, Florian T1 - HighPerMeshes - A Domain-Specific Language for Numerical Algorithms on Unstructured Grids JF - Euro-Par 2020: Parallel Processing Workshops. N2 - Solving partial differential equations on unstructured grids is a cornerstone of engineering and scientific computing. Nowadays, heterogeneous parallel platforms with CPUs, GPUs, and FPGAs enable energy-efficient and computationally demanding simulations. We developed the HighPerMeshes C++-embedded Domain-Specific Language (DSL) for bridging the abstraction gap between the mathematical and algorithmic formulation of mesh-based algorithms for PDE problems on the one hand and an increasing number of heterogeneous platforms with their different parallel programming and runtime models on the other hand. Thus, the HighPerMeshes DSL aims at higher productivity in the code development process for multiple target platforms. We introduce the concepts as well as the basic structure of the HighPer-Meshes DSL, and demonstrate its usage with three examples, a Poisson and monodomain problem, respectively, solved by the continuous finite element method, and the discontinuous Galerkin method for Maxwell’s equation. The mapping of the abstract algorithmic description onto parallel hardware, including distributed memory compute clusters is presented. Finally, the achievable performance and scalability are demonstrated for a typical example problem on a multi-core CPU cluster. Y1 - 2021 U6 - https://doi.org/10.1007/978-3-030-71593-9_15 SP - 185 EP - 196 PB - Springer ER - TY - JOUR A1 - Schneck, Jakob A1 - Weiser, Martin A1 - Wende, Florian T1 - Impact of mixed precision and storage layout on additive Schwarz smoothers JF - Numerical Linear Algebra with Applications N2 - The growing discrepancy between CPU computing power and memory bandwidth drives more and more numerical algorithms into a bandwidth-bound regime. One example is the overlapping Schwarz smoother, a highly effective building block for iterative multigrid solution of elliptic equations with higher order finite elements. Two options of reducing the required memory bandwidth are sparsity exploiting storage layouts and representing matrix entries with reduced precision in floating point or fixed point format. We investigate the impact of several options on storage demand and contraction rate, both analytically in the context of subspace correction methods and numerically at an example of solid mechanics. Both perspectives agree on the favourite scheme: fixed point representation of Cholesky factors in nested dissection storage. Y1 - 2021 U6 - https://doi.org/10.1002/nla.2366 VL - 28 IS - 4 ER - TY - GEN A1 - Schneck, Jakob A1 - Weiser, Martin A1 - Wende, Florian T1 - Impact of mixed precision and storage layout on additive Schwarz smoothers N2 - The growing discrepancy between CPU computing power and memory bandwidth drives more and more numerical algorithms into a bandwidth- bound regime. One example is the overlapping Schwarz smoother, a highly effective building block for iterative multigrid solution of elliptic equations with higher order finite elements. Two options of reducing the required memory bandwidth are sparsity exploiting storage layouts and representing matrix entries with reduced precision in floating point or fixed point format. We investigate the impact of several options on storage demand and contraction rate, both analytically in the context of subspace correction methods and numerically at an example of solid mechanics. Both perspectives agree on the favourite scheme: fixed point representation of Cholesky factors in nested dissection storage. T3 - ZIB-Report - 18-62 KW - higher order finite elements KW - mixed precision KW - overlapping Schwarz smoother Y1 - 2019 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:0297-zib-71305 SN - 1438-0064 ER - TY - CHAP A1 - Wende, Florian T1 - C++ Data Layout Abstractions through Proxy Types T2 - 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 14th International Workshop on Automatic Performance Tunings (iWAPT) N2 - Programs that process linearly indexed fields with structured element types in a data-parallel way usually suffer from the fact that compilers fail to generate efficient code if the selected data layout appears inappropriate for the chosen target architecture. If their internal heuristics cannot proof a performance gain from a data-parallel execution, compilers may fall back to scalar code generation. Data access through proxy types together with a customized container is one means to assist the compiler in generating efficient machine code in these cases without changing the user code. We present an automated proxy-type generator (using Clang’s LibTooling) and a configurable C++ container that supports different data layouts in a transparent way. Y1 - 2019 U6 - https://doi.org/10.1109/IPDPSW.2019.00126 SP - 758 EP - 767 ER - TY - JOUR A1 - Wende, Florian A1 - Marsman, Martijn A1 - Kim, Jeongnim A1 - Vasilev, Fedor A1 - Zhao, Zhengji A1 - Steinke, Thomas T1 - OpenMP in VASP: Threading and SIMD JF - International Journal of Quantum Chemistry N2 - The Vienna Ab initio Simulation Package (VASP) is a widely used electronic structure code that originally exploits process-level parallelism through the Message Passing Interface (MPI) for work distribution within and across nodes. Architectural changes of modern parallel processors urge programmers to address thread- and data-level parallelism as well to benefit most from the available compute resources within a node. We describe for VASP how to approach for an MPI + OpenMP parallelization including data-level parallelism through OpenMP SIMD constructs together with a generic high-level vector coding scheme. We can demonstrate an improved scalability of VASP and more than 20% gain over the MPI-only version, as well as a 2x increased performance of collective operations using the multiple-endpoint MPI feature. The high-level vector coding scheme applied to VASP's general gradient approximation routine gives up 9x performance gain on AVX512 platforms with the Intel compiler. Y1 - 2018 U6 - https://doi.org/10.1002/qua.25851 IS - Emerging Architectures in Computational Chemistry SP - e25851 PB - Wiley Online Library ER - TY - CHAP A1 - Zhao, Zhengji A1 - Marsman, Martijn A1 - Wende, Florian A1 - Kim, Jeongnim T1 - Performance of Hybrid MPI/OpenMP VASP on Cray XC40 Based on Intel Knights Landing Many Integrated Core Architecture N2 - With the recent installation of Cori, a Cray XC40 system with Intel Xeon Phi Knights Landing (KNL) many integrated core (MIC) architecture, NERSC is transitioning from the multi-core to the more energy-efficient many-core era. The developers of VASP, a widely used materials science code, have adopted MPI/OpenMP parallelism to better exploit the increased on-node parallelism, wider vector units, and the high bandwidth on-package memory (MCDRAM) of KNL. To achieve optimal performance, KNL specifics relevant for the build, boot and run time setup must be explored. In this paper, we present the performance analysis of representative VASP workloads on Cori, focusing on the effects of the compilers, libraries, and boot/run time options such as the NUMA/MCDRAM modes, Hyper-Threading, huge pages, core specialization, and thread scaling. The paper is intended to serve as a KNL performance guide for VASP users, but it will also benefit other KNL users. Y1 - 2017 N1 - Availability: https://cug.org/conference-proceedings ER - TY - CHAP A1 - Wende, Florian A1 - Marsman, Martijn A1 - Zhao, Zhengji A1 - Kim, Jeongnim T1 - Porting VASP from MPI to MPI+OpenMP [SIMD] T2 - Scaling OpenMP for Exascale Performance and Portability - 13th International Workshop on OpenMP, IWOMP 2017, Stony Brook, NY, USA, September 20-22, 2017 N2 - We describe for the VASP application (a widely used electronic structure code written in FORTRAN) the transition from an MPI-only to a hybrid code base leveraging the three relevant levels of parallelism to be addressed when optimizing for an effective execution on modern computer platforms: multiprocessing, multithreading and SIMD vectorization. To achieve code portability, we draw on MPI parallelization together with OpenMP threading and SIMD constructs. Combining the latter can be challenging in complex code bases. Optimization targets are combining multithreading and vectorization in different calling contexts as well as whole function vectorization. In addition to outlining design decisions made throughout the code transformation process, we will demonstrate the effectiveness of the code adaptations using different compilers (GNU, Intel) and target platforms (CPU, Intel Xeon Phi (KNL)). Y1 - 2017 U6 - https://doi.org/10.1007/978-3-319-65578-9_8 VL - 8766 SP - 107 EP - 122 ER - TY - CHAP A1 - Noack, Matthias A1 - Wende, Florian A1 - Zitzlsberger, Georg A1 - Klemm, Michael A1 - Steinke, Thomas T1 - KART - A Runtime Compilation Library for Improving HPC Application Performance T2 - High Performance Computing: ISC High Performance 2017 International Workshops, DRBSD, ExaComm, HCPM, HPC-IODC, IWOPH, IXPUG, P^3MA, VHPC, Visualization at Scale, WOPSSS, Frankfurt, Germany, June 18-22, 2017, Revised Selected Papers N2 - The effectiveness of ahead-of-time compiler optimization heavily depends on the amount of available information at compile time. Input-specific information that is only available at runtime cannot be used, although it often determines loop counts, branching predicates and paths, as well as memory-access patterns. It can also be crucial for generating efficient SIMD-vectorized code. This is especially relevant for the many-core architectures paving the way to exascale computing, which are more sensitive to code-optimization. We explore the design-space for using input-specific information at compile-time and present KART, a C++ library solution that allows developers tocompile, link, and execute code (e.g., C, C++ , Fortran) at application runtime. Besides mere runtime compilation of performance-critical code, KART can be used to instantiate the same code multiple times using different inputs, compilers, and options. Other techniques like auto-tuning and code-generation can be integrated into a KART-enabled application instead of being scripted around it. We evaluate runtimes and compilation costs for different synthetic kernels, and show the effectiveness for two real-world applications, HEOM and a WSM6 proxy. Y1 - 2017 U6 - https://doi.org/10.1007/978-3-319-67630-2_29 N1 - Best Paper Award VL - 10524 SP - 389 EP - 403 PB - Springer International Publishing ER - TY - JOUR A1 - Knoop, Helge A1 - Gronemeier, Tobias A1 - Sühring, Matthias A1 - Steinbach, Peter A1 - Noack, Matthias A1 - Wende, Florian A1 - Steinke, Thomas A1 - Knigge, Christoph A1 - Raasch, Siegfried A1 - Ketelsen, Klaus T1 - Porting the MPI-parallelized LES model PALM to multi-GPU systems and many integrated core processors: an experience report JF - International Journal of Computational Science and Engineering. Special Issue on: Novel Strategies for Programming Accelerators N2 - The computational power and availability of graphics processing units (GPUs), such as the Nvidia Tesla, and Many Integrated Core (MIC) processors, such as the Intel Xeon Phi, on high performance computing (HPC) systems is rapidly evolving. However, HPC applications need to be ported to take advantage of such hardware. This paper is a report on our experience of porting the MPI+OpenMP parallelised large-eddy simulation model (PALM) to multi-GPU as well as to MIC processor environments using the directive-based high level programming paradigm OpenACC and OpenMP, respectively. PALM is a Fortran-based computational fluid dynamics software package, used for the simulation of atmospheric and oceanic boundary layers to answer questions linked to fundamental atmospheric turbulence research, urban modelling, aircraft safety and cloud physics. Development of PALM started in 1997, the project currently entails 140 kLOC and is used on HPC farms of up to 43,200 cores. The main challenges we faced during the porting process are the size and complexity of the PALM code base, its inconsistent modularisation and the complete lack of a unit-test suite. We report the methods used to identify performance issues as well as our experiences with state-of-the-art profiling tools. Moreover, we outline the required porting steps in order to properly execute our code on GPUs and MIC processors, describe the problems and bottlenecks that we encountered during the porting process, and present separate performance tests for both architectures. These performance tests, however, do not provide any benchmark information that compares the performance of the ported code between the two architectures. Y1 - 2017 PB - Inderscience ET - Special Issue on: Novel Strategies for Programming Accelerators ER -