TY - CHAP A1 - Christgau, Steffen A1 - Everingham, Dylan A1 - Mikolajczak, Florian A1 - Schelten, Niklas A1 - Schnor, Bettina A1 - Schroetter, Max A1 - Stabernack, Benno A1 - Steinert, Fritjof T1 - Enabling Communication with FPGA-based Network-attached Accelerators for HPC Workloads T2 - Proceedings of the SC'23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis, SC-W 2023, Denver, CO, USA, November 12-17, 2023 N2 - The use of stand-alone, network-coupled Field Programmable Gate Array (FPGA) accelerators is intended to significantly increase the energy efficiency of HPC applications and thus also of HPC data centers. A loose coupling between the nodes of the HPC data center and the FPGAs is established through the high-speed network of the data center. This allows greater flexibility in combining different nodes and accelerators. Both the resulting energy savings and the increased flexibility through the network connection, enable the economical use of FPGAs. This work presents a communication stack to integrate the so-called Network-attached Accelerator (NAA) into the HPC data center. A low-level Remote Direct Memory Access (RDMA) Application Programming Interface (API) and a high-level Remote Procedure Call (RPC) API is designed on top of the RDMA over Converged Ethernet v2 (RoCEv2) communication stack. The experimental results over 100 Gbps RoCEv2 show that our design and implementation deliver performance close to the theoretical maximum. Y1 - 2023 U6 - https://doi.org/10.1145/3624062.3624540 SP - 530 EP - 538 PB - ACM ER - TY - CHAP A1 - Christgau, Steffen A1 - Dylan, Everingham A1 - Lübke, Max A1 - De Lucia, Marco A1 - Puhan, Danny A1 - Schelten, Niklas A1 - Schnor, Bettina A1 - Signer, Hannes A1 - Spazier, Johannes A1 - Stabernack, Benno A1 - Steinert, Fritjof A1 - Yahdzhyiev, Serhii T1 - On the Usability and Energy Efficiency of High-Level Synthesis for FPGA-based Network-Attached Accelerators T2 - 2025 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) N2 - Heterogeneity in high performance computing systems is one of the most promising approaches towards more energy-efficient computing on one hand and satisfying the raising demand of global computation capacity on the other hand. Besides the well-known key components like CPUs and GPGPUs are domain-specific accelerators like TPUs, FPGAs well known for their energy efficiency. This is especially true for highly specialized use cases. Network-attached accelerators promise more scalability and flexibility for FPGA usage in HPC environments. Easy and efficient programming of those accelerators is, however, still an open issue. Based on a framework for such accelerators which enables decoupling of FPGAs from their host system, we present a workflow using High-Level Synthesis (HLS) to offload application kernels to them. We evaluate this approach against a conventional Hardware Description Language (HDL) based workflow. In addition, we introduce the energy measurement tool EMA and assess the energy efficiency of both HLS and HDL design. Y1 - 2025 U6 - https://doi.org/10.1109/IPDPSW66978.2025.00139 SP - 886 EP - 895 ER -