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  <doc>
    <id>6513</id>
    <completedYear/>
    <publishedYear>2017</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition>Special Issue on: Novel Strategies for Programming Accelerators</edition>
    <issue/>
    <volume/>
    <type>article</type>
    <publisherName>Inderscience</publisherName>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>--</completedDate>
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    <title language="eng">Porting the MPI-parallelized LES model PALM to multi-GPU systems and many integrated core processors: an experience report</title>
    <abstract language="eng">The computational power and availability of graphics processing units (GPUs), such as the Nvidia Tesla, and Many Integrated Core (MIC) processors, such as the Intel Xeon Phi, on high performance computing (HPC) systems is rapidly evolving. However, HPC applications need to be ported to take advantage of such hardware. This paper is a report on our experience of porting the MPI+OpenMP parallelised large-eddy simulation model (PALM) to multi-GPU as well as to MIC processor environments using the directive-based high level programming paradigm OpenACC and OpenMP, respectively. PALM is a Fortran-based computational fluid dynamics software package, used for the simulation of atmospheric and oceanic boundary layers to answer questions linked to fundamental atmospheric turbulence research, urban modelling, aircraft safety and cloud physics. Development of PALM started in 1997, the project currently entails 140 kLOC and is used on HPC farms of up to 43,200 cores. The main challenges we faced during the porting process are the size and complexity of the PALM code base, its inconsistent modularisation and the complete lack of a unit-test suite. We report the methods used to identify performance issues as well as our experiences with state-of-the-art profiling tools. Moreover, we outline the required porting steps in order to properly execute our code on GPUs and MIC processors, describe the problems and bottlenecks that we encountered during the porting process, and present separate performance tests for both architectures. These performance tests, however, do not provide any benchmark information that compares the performance of the ported code between the two architectures.</abstract>
    <parentTitle language="eng">International Journal of Computational Science and Engineering. Special Issue on: Novel  Strategies for Programming Accelerators</parentTitle>
    <enrichment key="PeerReviewed">yes</enrichment>
    <enrichment key="SubmissionStatus">accepted for publication</enrichment>
    <enrichment key="AcceptedDate">2017-04-29</enrichment>
    <enrichment key="zib_relatedIdentifier">https://doi.org/10.1504/IJCSE.2017.10011396</enrichment>
    <enrichment key="AcceptedDate">2017-04-29</enrichment>
    <author>Helge Knoop</author>
    <submitter>Florian Wende</submitter>
    <author>Tobias Gronemeier</author>
    <author>Matthias Sühring</author>
    <author>Peter Steinbach</author>
    <author>Matthias Noack</author>
    <author>Florian Wende</author>
    <author>Thomas Steinke</author>
    <author>Christoph Knigge</author>
    <author>Siegfried Raasch</author>
    <author>Klaus Ketelsen</author>
    <collection role="institutes" number="vas">Distributed Algorithms and Supercomputing</collection>
    <collection role="persons" number="steinke">Steinke, Thomas</collection>
    <collection role="projects" number="2013-Many-Core-HPC">2013-Many-Core-HPC</collection>
  </doc>
  <doc>
    <id>6073</id>
    <completedYear/>
    <publishedYear/>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
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    <completedDate>--</completedDate>
    <publishedDate>2016-10-31</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">KART – A Runtime Compilation Library for Improving HPC Application Performance</title>
    <abstract language="eng">The effectiveness of ahead-of-time compiler optimization heavily depends on the amount of available information at compile time. Input-specific information that is only available at runtime cannot be used, although it often determines loop counts, branching predicates and paths, as well as memory-access patterns. It can also be crucial for generating efficient SIMD-vectorized code. This is especially relevant for the many-core architectures paving the way to exascale computing, which are more sensitive to code-optimization. We explore the design-space for using input-specific information at compile-time and present KART, a C++ library solution that allows developers to compile, link, and execute code (e.g., C, C++ , Fortran) at application runtime. Besides mere runtime compilation of performance-critical code, KART can be used to instantiate the same code multiple times using different inputs, compilers, and options. Other techniques like auto-tuning and code-generation can be integrated into a KART-enabled application instead of being scripted around it. We evaluate runtimes and compilation costs for different synthetic kernels, and show the effectiveness for two real-world applications, HEOM and a WSM6 proxy.</abstract>
    <identifier type="issn">1438-0064</identifier>
    <identifier type="urn">urn:nbn:de:0297-zib-60730</identifier>
    <identifier type="doi">10.1007/978-3-319-67630-2_29</identifier>
    <enrichment key="SourceTitle">Appeared in: ISC High Performance Workshops 2017: IXPUG Workshop "Experiences on Intel Knights Landing at the One Year Mark" LNCS 10524, 2017</enrichment>
    <author>Matthias Noack</author>
    <submitter>Matthias Noack</submitter>
    <author>Florian Wende</author>
    <author>Georg Zitzlsberger</author>
    <author>Michael Klemm</author>
    <author>Thomas Steinke</author>
    <series>
      <title>ZIB-Report</title>
      <number>16-48</number>
    </series>
    <collection role="institutes" number="vas">Distributed Algorithms and Supercomputing</collection>
    <collection role="persons" number="steinke">Steinke, Thomas</collection>
    <collection role="projects" number="2013-Many-Core-HPC">2013-Many-Core-HPC</collection>
    <file>https://opus4.kobv.de/opus4-zib/files/6073/kart_zr.pdf</file>
  </doc>
  <doc>
    <id>6054</id>
    <completedYear/>
    <publishedYear>2016</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume>Euro-Par 2016: Parallel Processing: 22nd International Conference on Parallel and Distributed Computing</volume>
    <type>conferenceobject</type>
    <publisherName>Springer International Publishing</publisherName>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>--</completedDate>
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    <title language="eng">Portable SIMD Performance with OpenMP* 4.x Compiler Directives</title>
    <abstract language="eng">Effective vectorization is becoming increasingly important for high performance and energy efficiency on processors with wide SIMD units. Compilers often require programmers to identify opportunities for vectorization, using directives to disprove data dependences. The OpenMP 4.x SIMD directives strive to provide portability. We investigate the ability of current compilers (GNU, Clang, and Intel) to generate SIMD code for microbenchmarks that cover common patterns in scientific codes and for two kernels from the VASP and the MOM5/ERGOM application. We explore coding strategies for improving SIMD performance across different compilers and platforms (Intel® Xeon® processor and Intel® Xeon Phi™ (co)processor). We compare OpenMP* 4.x SIMD vectorization with and without vector data types against SIMD intrinsics and C++ SIMD types. Our experiments show that in many cases portable performance can be achieved. All microbenchmarks are available as open source as a reference for programmers and compiler experts to enhance SIMD code generation.</abstract>
    <identifier type="isbn">978-3-319-43659-3</identifier>
    <identifier type="doi">10.1007/978-3-319-43659-3_20</identifier>
    <enrichment key="Series">LNCS</enrichment>
    <enrichment key="PeerReviewed">yes</enrichment>
    <editor>Pierre-Francois Dutot</editor>
    <submitter>Florian Wende</submitter>
    <author>Florian Wende</author>
    <editor>Denis Trystram</editor>
    <author>Matthias Noack</author>
    <author>Thomas Steinke</author>
    <author>Michael Klemm</author>
    <author>Georg Zitzlsberger</author>
    <author>Chris J. Newburn</author>
    <collection role="institutes" number="vas">Distributed Algorithms and Supercomputing</collection>
    <collection role="persons" number="steinke">Steinke, Thomas</collection>
    <collection role="projects" number="2013-Many-Core-HPC">2013-Many-Core-HPC</collection>
    <collection role="projects" number="2013-SECOS">2013-SECOS</collection>
  </doc>
  <doc>
    <id>6919</id>
    <completedYear/>
    <publishedYear>2018</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>947</pageFirst>
    <pageLast>956</pageLast>
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    <type>conferenceobject</type>
    <publisherName/>
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    <completedDate>--</completedDate>
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    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">DM-HEOM: A Portable and Scalable Solver-Framework for the Hierarchical Equations of Motion</title>
    <abstract language="eng">Computing the Hierarchical Equations of Motion (HEOM) is by itself a challenging problem, and so is writing portable production code that runs efficiently on a variety of architectures while scaling from PCs to supercomputers. We combined both challenges to push the boundaries of simulating quantum systems, and to evaluate and improve methodologies for scientific software engineering.&#13;
Our contributions are threefold: We present the first distributed memory implementation of the HEOM method (DM-HEOM), we describe an interdisciplinary development workflow, and we provide guidelines and experiences for designing distributed, performance-portable HPC applications with MPI-3, OpenCL and other state-of-the-art programming models. We evaluated the resulting code on multi- and many-core CPUs as well as GPUs, and demonstrate scalability on a Cray XC40 supercomputer for the PS I molecular light harvesting complex.</abstract>
    <parentTitle language="eng">2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 19th IEEE Int. Workshop on Parallel and Distributed Scientific and Engineering Computing (PDSEC 2018)</parentTitle>
    <identifier type="doi">10.1109/IPDPSW.2018.00149</identifier>
    <identifier type="isbn">978-1-5386-5555-9</identifier>
    <note>Best Paper Award</note>
    <enrichment key="PeerReviewed">yes</enrichment>
    <enrichment key="AcceptedDate">2018-03-03</enrichment>
    <author>Matthias Noack</author>
    <submitter>Matthias Noack</submitter>
    <author>Alexander Reinefeld</author>
    <author>Tobias Kramer</author>
    <author>Thomas Steinke</author>
    <collection role="institutes" number="vas">Distributed Algorithms and Supercomputing</collection>
    <collection role="persons" number="reinefeld">Reinefeld, Alexander</collection>
    <collection role="persons" number="steinke">Steinke, Thomas</collection>
    <collection role="projects" number="2013-Many-Core-HPC">2013-Many-Core-HPC</collection>
    <collection role="persons" number="kramer">Kramer, Tobias</collection>
    <collection role="projects" number="2015-HEOM">2015-HEOM</collection>
  </doc>
  <doc>
    <id>6514</id>
    <completedYear/>
    <publishedYear>2017</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>389</pageFirst>
    <pageLast>403</pageLast>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume>10524</volume>
    <type>bookpart</type>
    <publisherName>Springer International Publishing</publisherName>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2017-10-20</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">KART - A Runtime Compilation Library for Improving HPC Application Performance</title>
    <abstract language="eng">The effectiveness of ahead-of-time compiler optimization heavily depends on the amount of available information at compile time. Input-specific information that is only available at runtime cannot be used, although it often determines loop counts, branching predicates and paths, as well as memory-access patterns. It can also be crucial for generating efficient SIMD-vectorized code. This is especially relevant for the many-core architectures paving the way to exascale computing, which are more sensitive to code-optimization. We explore the design-space for using input-specific information at compile-time and present KART, a C++ library solution that allows developers tocompile, link, and execute code (e.g., C, C++ , Fortran) at application runtime. Besides mere runtime compilation of performance-critical code, KART can be used to instantiate the same code multiple times using different inputs, compilers, and options. Other techniques like auto-tuning and code-generation can be integrated into a KART-enabled application instead of being scripted around it. We evaluate runtimes and compilation costs for different synthetic kernels, and show the effectiveness for two real-world applications, HEOM and a WSM6 proxy.</abstract>
    <parentTitle language="eng">High Performance Computing: ISC High Performance 2017 International Workshops, DRBSD, ExaComm, HCPM, HPC-IODC, IWOPH, IXPUG, P^3MA, VHPC, Visualization at Scale, WOPSSS, Frankfurt, Germany, June 18-22, 2017, Revised Selected Papers</parentTitle>
    <identifier type="doi">10.1007/978-3-319-67630-2_29</identifier>
    <note>Best Paper Award</note>
    <enrichment key="Series">LNCS</enrichment>
    <enrichment key="PeerReviewed">yes</enrichment>
    <enrichment key="PreprintUrn">urn:nbn:de:0297-zib-60730</enrichment>
    <author>Matthias Noack</author>
    <submitter>Florian Wende</submitter>
    <author>Florian Wende</author>
    <author>Georg Zitzlsberger</author>
    <author>Michael Klemm</author>
    <author>Thomas Steinke</author>
    <collection role="institutes" number="vas">Distributed Algorithms and Supercomputing</collection>
    <collection role="persons" number="steinke">Steinke, Thomas</collection>
    <collection role="projects" number="2013-Many-Core-HPC">2013-Many-Core-HPC</collection>
  </doc>
  <doc>
    <id>7350</id>
    <completedYear/>
    <publishedYear>2019</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>--</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Heterogeneous Active Messages for Offloading on the NEC SX-Aurora TSUBASA</title>
    <abstract language="eng">The NEC SX-Aurora TSUBASA is a new generation of vector processing architectures that combines a standard Intel Xeon host with the newly developed NEC Vector Engine co-processor cards. One way to use these co-processors is offloading suitable parts of the program from the host to the Vector Engines. Currently, the only vendor-provided offloading solutions are the low-level Vector Engine Offloading (VEO) library, and a builtin reverse-offloading mechanism named VHcall.&#13;
In this work, we extend the portable Heterogeneous Active Messages (HAM) based HAM-Offload framework with support for the NEC SX-Aurora TSUBASA. Therefore, we design, implement, and evaluate two messaging protocols aimed at minimising offloading cost. This sheds some light on how to achieve fast communication between host CPU and the Vector Engines of the NEC SX-Aurora TSUBASA. Compared with VEO, the DMA-based protocol reduces offloading overhead by a factor of 13×. The resulting framework enables users to write portable offload applications with low overhead, that do neither require a language extension like OpenMP, nor a special language like OpenCL. Existing HAM-Offload applications are now ready to run on the NEC SX-Aurora TSUBASA.</abstract>
    <parentTitle language="eng">2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Heterogeneity in Computing Workshop (HCW 2019)</parentTitle>
    <enrichment key="PeerReviewed">yes</enrichment>
    <enrichment key="AcceptedDate">2019-03-06</enrichment>
    <author>Matthias Noack</author>
    <submitter>Matthias Noack</submitter>
    <author>Erich Focht</author>
    <author>Thomas Steinke</author>
    <collection role="institutes" number="vas">Distributed Algorithms and Supercomputing</collection>
    <collection role="persons" number="steinke">Steinke, Thomas</collection>
    <collection role="projects" number="2013-Many-Core-HPC">2013-Many-Core-HPC</collection>
  </doc>
  <doc>
    <id>5514</id>
    <completedYear/>
    <publishedYear>2015</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>--</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Application Performance on a Cray XC30 Evaluation System with Xeon Phi Coprocessors at HLRN-III</title>
    <parentTitle language="eng">Cray User Group</parentTitle>
    <enrichment key="PeerReviewed">yes</enrichment>
    <author>Florian Wende</author>
    <submitter>Florian Schintke</submitter>
    <author>Matthias Noack</author>
    <author>Thorsten Schütt</author>
    <author>Stephen Sachs</author>
    <author>Thomas Steinke</author>
    <collection role="institutes" number="vas">Distributed Algorithms and Supercomputing</collection>
    <collection role="persons" number="schuett">Schütt, Thorsten</collection>
    <collection role="persons" number="steinke">Steinke, Thomas</collection>
    <collection role="projects" number="2013-Many-Core-HPC">2013-Many-Core-HPC</collection>
  </doc>
  <doc>
    <id>5134</id>
    <completedYear/>
    <publishedYear>2014</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>--</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">A Unified Programming Model for Intra- and Inter-Node Offloading on Xeon Phi Clusters</title>
    <abstract language="eng">Standard offload programming models for the Xeon Phi, e.g. Intel LEO and OpenMP 4.0, are restricted to a single compute node and hence a limited number of coprocessors. Scaling applications across a Xeon Phi cluster/supercomputer thus requires hybrid programming approaches, usually MPI+X. In this work, we present a framework based on heterogeneous active messages (HAM-Offload) that provides the means to offload work to local and remote (co)processors using a unified offload API. Since HAM-Offload provides similar primitives as current local offload frameworks, existing applications can be easily ported to overcome the single-node limitation while keeping the convenient offload programming model. We demonstrate the effectiveness of the framework by using it to enable a real-world application from the field of molecular dynamics to use multiple local and remote Xeon Phis. The evaluation shows good scaling behavior. Compared with LEO, performance is equal for large offloads and significantly better for small offloads.</abstract>
    <parentTitle language="eng">SC '14: Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis. SC14, November 16-21, 2014, New Orleans, Louisiana, USA</parentTitle>
    <identifier type="url">http://dl.acm.org/citation.cfm?id=2683616</identifier>
    <identifier type="doi">10.1109/SC.2014.22</identifier>
    <enrichment key="PeerReviewed">yes</enrichment>
    <author>Matthias Noack</author>
    <submitter>Regine Kossick</submitter>
    <author>Florian Wende</author>
    <author>Thomas Steinke</author>
    <author>Frank Cordes</author>
    <collection role="institutes" number="vas">Distributed Algorithms and Supercomputing</collection>
    <collection role="persons" number="steinke">Steinke, Thomas</collection>
    <collection role="projects" number="2013-Many-Core-HPC">2013-Many-Core-HPC</collection>
  </doc>
  <doc>
    <id>5797</id>
    <completedYear/>
    <publishedYear>2016</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>--</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Fast In-Memory Checkpointing with POSIX API for Legacy Exascale-Applications</title>
    <parentTitle language="eng">SPPEXA Symposium 2016</parentTitle>
    <identifier type="doi">10.1007/978-3-319-40528-5_19</identifier>
    <enrichment key="PeerReviewed">yes</enrichment>
    <author>J. Fajerski</author>
    <submitter>Florian Schintke</submitter>
    <author>Matthias Noack</author>
    <author>Alexander Reinefeld</author>
    <author>Florian Schintke</author>
    <author>Thorsten Schütt</author>
    <author>Thomas Steinke</author>
    <collection role="institutes" number="vas">Distributed Algorithms and Supercomputing</collection>
    <collection role="persons" number="reinefeld">Reinefeld, Alexander</collection>
    <collection role="persons" number="schintke">Schintke, Florian</collection>
    <collection role="persons" number="schuett">Schütt, Thorsten</collection>
    <collection role="persons" number="steinke">Steinke, Thomas</collection>
    <collection role="projects" number="2006-XtreemFS">2006-XtreemFS</collection>
    <collection role="projects" number="2013-FFMK">2013-FFMK</collection>
  </doc>
  <doc>
    <id>8250</id>
    <completedYear/>
    <publishedYear>2021</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>--</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Performance Evaluation and Improvements of the PoCL Open-Source OpenCL Implementation on Intel CPUs</title>
    <abstract language="eng">The Portable Computing Language (PoCL) is a vendor independent open-source OpenCL implementation that aims to support a variety of compute devices in a single platform. Evaluating PoCL versus the Intel OpenCL implementation reveals significant performance drawbacks of PoCL on Intel CPUs – which run 92 % of the TOP500 list. Using a selection of benchmarks, we identify and analyse performance issues in PoCL with a focus on scheduling and vectorisation. We propose a new CPU device-driver based on Intel Threading Building Blocks (TBB), and evaluate LLVM with respect to automatic compiler vectorisation across work-items in PoCL. Using the TBB driver, it is possible to narrow the gap to Intel OpenCL and even outperform it by a factor of up to 1.3× in our proxy application benchmark with a manual vectorisation strategy.</abstract>
    <parentTitle language="eng">IWOCL'21: International Workshop on OpenCL</parentTitle>
    <identifier type="doi">10.1145/3456669.3456698</identifier>
    <enrichment key="PeerReviewed">yes</enrichment>
    <enrichment key="AcceptedDate">2021-03-03</enrichment>
    <enrichment key="opus.source">publish</enrichment>
    <author>Tobias Baumann</author>
    <submitter>Tobias Baumann</submitter>
    <author>Matthias Noack</author>
    <author>Thomas Steinke</author>
    <collection role="institutes" number="vas">Distributed Algorithms and Supercomputing</collection>
    <collection role="persons" number="steinke">Steinke, Thomas</collection>
    <collection role="projects" number="MATHEON-A17">MATHEON-A17</collection>
    <collection role="institutes" number="PaDC">Parallel and Distributed Computing</collection>
  </doc>
</export-example>
