@inproceedings{KnaustSeilerReinertetal., author = {Knaust, Marius and Seiler, Enrico and Reinert, Knut and Steinke, Thomas}, title = {Co-Design for Energy Efficient and Fast Genomic Search: Interleaved Bloom Filter on FPGA}, series = {FPGA '22: Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays}, booktitle = {FPGA '22: Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays}, doi = {10.1145/3490422.3502366}, pages = {180 -- 189}, abstract = {Next-Generation Sequencing technologies generate a vast and exponentially increasing amount of sequence data. The Interleaved Bloom Filter (IBF) is a novel indexing data structure which is state-of-the-art for distributing approximate queries with an in-memory data structure. With it, a main task of sequence analysis pipelines, (approximately) searching large reference data sets for sequencing reads or short sequence patterns like genes, can be significantly accelerated. To meet performance and energy-efficiency requirements, we chose a co-design approach of the IBF data structure on the FPGA platform. Further, our OpenCL-based implementation allows a seamless integration into the widely used SeqAn C++ library for biological sequence analysis. Our algorithmic design and optimization strategy takes advantage of FPGA-specific features like shift register and the parallelization potential of many bitwise operations. We designed a well-chosen schema to partition data across the different memory domains on the FPGA platform using the Shared Virtual Memory concept. We can demonstrate significant improvements in energy efficiency of up to 19x and in performance of up to 5.6x, respectively, compared to a well-tuned, multithreaded CPU reference.}, language = {en} } @inproceedings{KnaustMayerSteinke, author = {Knaust, Marius and Mayer, Florian and Steinke, Thomas}, title = {OpenMP to FPGA Offloading Prototype Using OpenCL SDK}, series = {2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}, booktitle = {2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}, doi = {10.1109/IPDPSW.2019.00072}, pages = {387 -- 390}, abstract = {Field-programmable gate arrays (FPGAs) are of great interest for future high-performance computing and data analytics systems, since they are capable of efficient, highly-parallel data processing. Even though high-level synthesis became more popular in the last years, the effort of porting existing scientific software onto FPGAs is still considerable. We propose to use OpenMP target offloading as a solution, which we implement in a first prototype, making use of the preexisting OpenCL SDK of the FPGA vendor. Early results demonstrate the feasibility of this approach and also reveal that further optimizations will be necessary such that code can be written in an FPGA-agnostic way.}, language = {en} } @inproceedings{MayerKnaustPhilippsen, author = {Mayer, Florian and Knaust, Marius and Philippsen, Michael}, title = {OpenMP on FPGAs—A Survey}, series = {OpenMP: Conquering the Full Hardware Spectrum}, booktitle = {OpenMP: Conquering the Full Hardware Spectrum}, doi = {10.1007/978-3-030-28596-8_7}, pages = {94 -- 108}, abstract = {Due to the ubiquity of OpenMP and the rise of FPGA-based accelerators in the HPC world, several research groups have attempted to bring the two together by building OpenMP-to-FPGA compilers. This paper is a survey of the current state of the art (with a focus on the OpenMP target pragma). It first introduces and explains a design space for the compilers. Design space dimensions include how FPGA infrastructure is generated, how work is distributed, and where/how target outlining is done. A table concisely condenses the available information on the surveyed projects which are also summarized and compared. The paper concludes with possible future research directions.}, language = {en} } @inproceedings{ChristgauKnaustSteinke, author = {Christgau, Steffen and Knaust, Marius and Steinke, Thomas}, title = {A First Step towards Support for MPI Partitioned Communication on SYCL-programmed FPGAs}, series = {IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing, H2RC@SC 2022, Dallas, TX, USA, November 13-18, 2022}, booktitle = {IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing, H2RC@SC 2022, Dallas, TX, USA, November 13-18, 2022}, publisher = {IEEE}, doi = {10.1109/H2RC56700.2022.00007}, pages = {9 -- 17}, abstract = {Version 4.0 of the Message Passing Interface standard introduced the concept of Partitioned Communication which adds support for multiple contributions to a communication buffer. Although initially targeted at multithreaded MPI applications, Partitioned Communication currently receives attraction in the context of accelerators, especially GPUs. In this publication it is demonstrated that this communication concept can also be implemented for SYCL-programmed FPGAs. This includes a discussion of the design space and the presentation of a prototypical implementation. Experimental results show that a lightweight implementation on top of an existing MPI library is possible. In addition, the presented approach also reveals issues in both the SYCL and the MPI standard which need to be addresses for improved support of the intended communication style.}, language = {en} }