@inproceedings{ChristgauDylanLuebkeetal.2025, author = {Christgau, Steffen and Dylan, Everingham and L{\"u}bke, Max and De Lucia, Marco and Puhan, Danny and Schelten, Niklas and Schnor, Bettina and Signer, Hannes and Spazier, Johannes and Stabernack, Benno and Steinert, Fritjof and Yahdzhyiev, Serhii}, title = {On the Usability and Energy Efficiency of High-Level Synthesis for FPGA-based Network-Attached Accelerators}, booktitle = {2025 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}, doi = {10.1109/IPDPSW66978.2025.00139}, pages = {886 -- 895}, year = {2025}, abstract = {Heterogeneity in high performance computing systems is one of the most promising approaches towards more energy-efficient computing on one hand and satisfying the raising demand of global computation capacity on the other hand. Besides the well-known key components like CPUs and GPGPUs are domain-specific accelerators like TPUs, FPGAs well known for their energy efficiency. This is especially true for highly specialized use cases. Network-attached accelerators promise more scalability and flexibility for FPGA usage in HPC environments. Easy and efficient programming of those accelerators is, however, still an open issue. Based on a framework for such accelerators which enables decoupling of FPGAs from their host system, we present a workflow using High-Level Synthesis (HLS) to offload application kernels to them. We evaluate this approach against a conventional Hardware Description Language (HDL) based workflow. In addition, we introduce the energy measurement tool EMA and assess the energy efficiency of both HLS and HDL design.}, language = {en} }