@inproceedings{FajerskiNoackReinefeldetal.2016, author = {Fajerski, J. and Noack, Matthias and Reinefeld, Alexander and Schintke, Florian and Sch{\"u}tt, Thorsten and Steinke, Thomas}, title = {Fast In-Memory Checkpointing with POSIX API for Legacy Exascale-Applications}, booktitle = {SPPEXA Symposium 2016}, doi = {10.1007/978-3-319-40528-5_19}, year = {2016}, language = {en} } @article{AlhaddadFoerstnerGrothetal.2022, author = {Alhaddad, Samer and F{\"o}rstner, Jens and Groth, Stefan and Gr{\"u}newald, Daniel and Grynko, Yevgen and Hannig, Frank and Kenter, Tobias and Pfreundt, F.J. and Plessl, Christian and Schotte, Merlind and Steinke, Thomas and Teich, J. and Weiser, Martin and Wende, Florian}, title = {The HighPerMeshes Framework for Numerical Algorithms on Unstructured Grids}, volume = {34}, journal = {Concurrency and Computation: Practice and Experience}, number = {14}, doi = {10.1002/cpe.6616}, year = {2022}, abstract = {Solving PDEs on unstructured grids is a cornerstone of engineering and scientific computing. Heterogeneous parallel platforms, including CPUs, GPUs, and FPGAs, enable energy-efficient and computationally demanding simulations. In this article, we introduce the HPM C++-embedded DSL that bridges the abstraction gap between the mathematical formulation of mesh-based algorithms for PDE problems on the one hand and an increasing number of heterogeneous platforms with their different programming models on the other hand. Thus, the HPM DSL aims at higher productivity in the code development process for multiple target platforms. We introduce the concepts as well as the basic structure of the HPM DSL, and demonstrate its usage with three examples. The mapping of the abstract algorithmic description onto parallel hardware, including distributed memory compute clusters, is presented. A code generator and a matching back end allow the acceleration of HPM code with GPUs. Finally, the achievable performance and scalability are demonstrated for different example problems.}, language = {en} } @inproceedings{ChristgauKnaustSteinke2022, author = {Christgau, Steffen and Knaust, Marius and Steinke, Thomas}, title = {A First Step towards Support for MPI Partitioned Communication on SYCL-programmed FPGAs}, booktitle = {IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing, H2RC@SC 2022, Dallas, TX, USA, November 13-18, 2022}, publisher = {IEEE}, doi = {10.1109/H2RC56700.2022.00007}, pages = {9 -- 17}, year = {2022}, abstract = {Version 4.0 of the Message Passing Interface standard introduced the concept of Partitioned Communication which adds support for multiple contributions to a communication buffer. Although initially targeted at multithreaded MPI applications, Partitioned Communication currently receives attraction in the context of accelerators, especially GPUs. In this publication it is demonstrated that this communication concept can also be implemented for SYCL-programmed FPGAs. This includes a discussion of the design space and the presentation of a prototypical implementation. Experimental results show that a lightweight implementation on top of an existing MPI library is possible. In addition, the presented approach also reveals issues in both the SYCL and the MPI standard which need to be addresses for improved support of the intended communication style.}, language = {en} } @inproceedings{BrookFullerSwinburneetal.2022, author = {Brook, Glenn and Fuller, Douglas and Swinburne, John and Christgau, Steffen and L{\"a}uter, Matthias and Rodrigues Pel{\´a}, Ronaldo and Lewin, Stein and Christian, Tuma and Steinke, Thomas}, title = {An Early Scalability Study of Omni-Path Express}, address = {Hamburg}, organization = {ISC 2022 IXPUG}, doi = {10.13140/RG.2.2.21353.57442}, pages = {8}, year = {2022}, abstract = {This work provides a brief description of Omni-Path Express and the current status of its development, stability, and performance. Basic benchmarks that highlight the gains of OPX over PSM2 are provided, and the results of an initial performance and scalability study of several applications are presented.}, language = {en} } @inproceedings{KnaustSeilerReinertetal.2022, author = {Knaust, Marius and Seiler, Enrico and Reinert, Knut and Steinke, Thomas}, title = {Co-Design for Energy Efficient and Fast Genomic Search: Interleaved Bloom Filter on FPGA}, booktitle = {FPGA '22: Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays}, doi = {10.1145/3490422.3502366}, pages = {180 -- 189}, year = {2022}, abstract = {Next-Generation Sequencing technologies generate a vast and exponentially increasing amount of sequence data. The Interleaved Bloom Filter (IBF) is a novel indexing data structure which is state-of-the-art for distributing approximate queries with an in-memory data structure. With it, a main task of sequence analysis pipelines, (approximately) searching large reference data sets for sequencing reads or short sequence patterns like genes, can be significantly accelerated. To meet performance and energy-efficiency requirements, we chose a co-design approach of the IBF data structure on the FPGA platform. Further, our OpenCL-based implementation allows a seamless integration into the widely used SeqAn C++ library for biological sequence analysis. Our algorithmic design and optimization strategy takes advantage of FPGA-specific features like shift register and the parallelization potential of many bitwise operations. We designed a well-chosen schema to partition data across the different memory domains on the FPGA platform using the Shared Virtual Memory concept. We can demonstrate significant improvements in energy efficiency of up to 19x and in performance of up to 5.6x, respectively, compared to a well-tuned, multithreaded CPU reference.}, language = {en} } @inproceedings{BaumannNoackSteinke2021, author = {Baumann, Tobias and Noack, Matthias and Steinke, Thomas}, title = {Performance Evaluation and Improvements of the PoCL Open-Source OpenCL Implementation on Intel CPUs}, booktitle = {IWOCL'21: International Workshop on OpenCL}, doi = {10.1145/3456669.3456698}, year = {2021}, abstract = {The Portable Computing Language (PoCL) is a vendor independent open-source OpenCL implementation that aims to support a variety of compute devices in a single platform. Evaluating PoCL versus the Intel OpenCL implementation reveals significant performance drawbacks of PoCL on Intel CPUs - which run 92 \% of the TOP500 list. Using a selection of benchmarks, we identify and analyse performance issues in PoCL with a focus on scheduling and vectorisation. We propose a new CPU device-driver based on Intel Threading Building Blocks (TBB), and evaluate LLVM with respect to automatic compiler vectorisation across work-items in PoCL. Using the TBB driver, it is possible to narrow the gap to Intel OpenCL and even outperform it by a factor of up to 1.3× in our proxy application benchmark with a manual vectorisation strategy.}, language = {en} }