2026-09-20T01:12:47Z https://opus4.kobv.de/opus4-uni-passau/oai

oai:kobv.de-opus4-uni-passau:422 2025-08-13 bibliography:false doc-type:PhDThesis open_access ddc ddc:004

Delay Testing in Nanoscale Technology under Process Variations Jie Jiang 004 CMOS Digital CMOS IC Test Power Noise Simulation Parameter variations Small-delay testing K longest path generation In modern CMOS technology, process variations have significantly increased impact on the circuit behavior with continuously scaled transistor sizes. Manufactured devices tend to have different performances due to parameter variations during manufacturing and in the operating context. Conventional tests generated regardless of variations could fail to rule out devices with low performance and even functional failure caused by extreme variations; the unreliability in shipped products is in turn raised. To tackle the problem, many existing test approaches have focused on identifying and testing a number of critical paths in the circuit, and aimed at the efficiency of the searching process. However, the statistical circuit model, which better describes the circuit timing behavior under variations, is not yet sufficiently investigated and employed by existing testing methodologies. This thesis work proposes Opt-KLPG and MIRID, which can be utilized by a statistical delay testing flow. Opt-KLPG—a K Longest Paths Generation (KLPG) algorithm for optimal solutions under memory constraints—can pin-pointedly generate tests for small delay defects, which are common small timing deviations under process variations, based on the traditional KLPG algorithm. In contrast to KLPG, Opt-KLPG guarantees the optimality of the solution (the K longest sensitizable paths indeed). MIRID is a mixed-mode timing-aware simulator, incorporating effects of power-supply noise and combining an event-driven logic simulation engine with interfaces to provided electrical models. MIRID aims at evaluating delay tests in presence of process variations efficiently yet accurately, by performing logic simulation at the gate level while determining the gate delays using simplified electrical modes. The electrical models applied by the simulator focus on the IR drop effect. Electrical parameters mainly contributing to the effect are incorporated into the model. The simulator is generic and flexible to be adapted by modifying the interfaces with minor effort. Both applications were verified in various aspects by experiments for academical/industrial circuits, and turned out to have satisfiable effectiveness and performance. Universität Passau Passau Innstrasse 29, 94032 Passau Ilia Polian Prof. Dr. Joan Figueras Prof. Dr. 2016-11-09 2016-11-15 PhDThesis Text urn:nbn:de:bvb:739-opus4-4229 application/pdf eng Standardbedingung laut Einverständniserklärung thesis.doctoral Universität Passau Passau Fakultät für Informatik und Mathematik 1 https://opus4.kobv.de/opus4-uni-passau/oai/container/index/docId/422 https://opus4.kobv.de/opus4-uni-passau/frontdoor/index/index/docId/422