Fachbereich Ingenieur- und Naturwissenschaften
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Micro-Transfer printing (µTP) is a promising technique for hetero-integration of III-V materials into Si-based photonic platforms. To enhance the print yield by increasing the adhesion between the III-V material and Si or SiO2 surface, an adhesion promoter like Benzocyclobutene is typically used as interlayer. In this work, we demonstrate µTP of InP based coupons on SiO2 interlayer without any adhesive interlayer and investigate the mechanism of adhesive free bonding. Source coupons are InP-based coupon stacks on a sacrificial layer that is removed by a chemical wet etch with FeCl3. For the target we fabricated amorphous-Si waveguides on 8” wafer encapsulated by a High Density Plasma SiO2 which was planarized by a chemical mechanical polishing procedure. We used O2 plasma to activate both source and target to increase adhesion between coupon and substrate. To get a better understanding of the bonding mechanism we applied several surface characterization methods. Root mean square roughness of InP and SiO2 was measured by atomic force microscopy before and after plasma activation. The step height of the micro-transfer printed source coupon on the target wafer is estimated by optical step profiler. We used Raman peak position mappings of InP to analyze possible strain and contact angle measurements on SiO2, before and after plasma activation to observe a change in the hydrophilicity of the surface. X-ray Photoelectron Spectroscopy analysis was used to characterize the surface energy states of P2p, In3d, O1s for InP source and Si2p, O1s for SiO2 target. Our results demonstrate direct bonding of InP coupons by means of µTP without the need of a strain-compensation layer. In this way, a promising route towards Complementary Metal-Oxide-Semiconductor compatible use of µTP for the hetero-integration of InP is provided.
The two main features of the memristive devices which makes them the promising candidates for neuromorphic applications are low power consumption and CMOS compatibility. The monolithic integration of memristive devices with CMOS circuitry paves the way for in-memory computing. This chapter focuses on the factors governing the CMOS integration process. Firstly, the influence of CMOS baseline technology selection on the memristor module is briefly discussed. Secondly, the selection of metal level interconnects and their effect on the memristive device performance is explained. Further, the widely used deposition technique for the CMOS compatible memristive switching layers is presented. Finally, the implementation of the optimized process for the fabrication of the memristive module and its influence on the device performance is presented in terms of electrical characterization results.
Dislocation free local SiGe-on-insulator (SGOI) virtual substrate is fabricated using lateral selective SiGe growth by reduced pressure chemical vapor deposition. The lateral selective SiGe growth is performed around a ∼1.25 μm square Si (001) pillar in a cavity formed by HCl vapor phase etching of Si at 850 °C from side of SiO2/Si mesa structure on buried oxide. Smooth root mean square roughness of SiGe surface of 0.14 nm, which is determined by interface roughness between the sacrificially etched Si and the SiO2 cap, is obtained. Uniform Ge content of ∼40% in the laterally grown SiGe is observed. In the Si pillar, tensile strain of ∼0.65% is found which could be due to thermal expansion difference between SiO2 and Si. In the SiGe, tensile strain of ∼1.4% along 〈010〉 direction, which is higher compared to that along 〈110〉 direction, is observed. The tensile strain is induced from both [110] and [−110] directions. Threading dislocations in the SiGe are located only ∼400 nm from Si pillar and stacking faults are running towards 〈110〉 directions, resulting in the formation of a wide dislocation-free area in SiGe along 〈010〉 due to horizontal aspect ratio trapping.
Silicon photonic micro-ring resonators (MRR) developed on the silicon-on-insulator (SOI) platform, owing to their high sensitivity and small footprint, show great potential for many chemical and biological sensing applications such as label-free detection in environmental monitoring, biomedical engineering, and food analysis. In this tutorial, we provide the theoretical background and give design guidelines for SOI-based MRR as well as examples of surface functionalization procedures for label-free detection of molecules.
After introducing the advantages and perspectives of MRR, fundamentals of MRR are described in detail, followed by an introduction to the fabrication methods, which are based on a complementary metal-oxide semiconductor (CMOS) technology. Optimization of MRR for chemical and biological sensing is provided, with special emphasis on the optimization of waveguide geometry. At this point, the difference between chemical bulk sensing and label-free surface sensing is explained, and definitions like waveguide sensitivity, ring sensitivity, overall sensitivity as well as the limit of detection (LoD) of MRR are introduced. Further, we show and explain chemical bulk sensing of sodium chloride (NaCl) in water and provide a recipe for label-free surface sensing.
From Lab-on-chip to Lab-in-App: Challenges towards silicon photonic biosensors product developments
(2022)
This work presents and evaluates different approaches of integrated optical sensors based on photonic integrated circuit (PIC) technologies for refractive index sensing. Bottlenecks in the fabrication flow towards an applicable system are discussed that hinder a cost-effective mass-production for disposable sensor chips. As sensor device, a waveguide coupled micro-ring based approach is chosen which is manufactured in an 8” wafer level process. We will show that the co-integration with a reproducible, scalable and low-cost microfluidic interface is the main challenge which needs to be overcome for future application of silicon technology based PIC sensor chips.
The possibility of exploiting the enormous potential of graphene for microelectronics and photonics must go through the optimization of the graphene–metal contact. Achieving low contact resistance is essential for the consideration of graphene as a candidate material for electronic and photonic devices. This work has been carried out in an 8′′ wafer pilot-line for the integration of graphene into a CMOS environment. The main focus is to study the impact of the patterning of graphene and passivation on metal–graphene contact resistance. The latter is measured by means of transmission line measurement (TLM) with several contact designs. The presented approaches enable reproducible formation of contact resistivity as low as 660 Ω μm with a sheet resistance of 1.8 kΩ/□ by proper graphene patterning, passivation of the channel and a post-processing treatment such as annealing.
The resistive switching properties of HfO₂ based 1T-1R memristive devices are electrically modified by adding ultra-thin layers of Al₂O₃ into the memristive device. Three different types of memristive stacks are fabricated in the 130 nm CMOS technology of IHP. The switching properties of the memristive devices are discussed with respect to forming voltages, low resistance state and high resistance state characteristics and their variabilities. The experimental I–V characteristics of set and reset operations are evaluated by using the quantum point contact model. The properties of the conduction filament in the on and off states of the memristive devices are discussed with respect to the model parameters obtained from the QPC fit.
Comprehensive diagnostics is a prerequisite for the application of graphene in semiconductor technologies. Here, the authors present long-term investigations of graphene on 200-mm Ge(100)/Si(100) wafers under clean room environmental conditions. Diagnostic of graphene was performed by a fast and nondestructive metrology method based on the combination of spectroscopic ellipsometry and reflectometry (SE/R), realized within a wafer optical metrology tool. A robust procedure for unambiguous thickness monitoring of a multilayer film stack, including graphene, interface layer GeOx underneath graphene, and surface roughness is developed and applied for process control. The authors found a relationship between the quality of graphene and the growth of GeOx beneath graphene. Enhanced oxidation of Ge beneath graphene was registered as a long-term process. SE/R measurements were validated and complemented using atomic force microscopy, scanning electron microscopy, Raman spectroscopy, and secondary ion mass spectrometry. This comparative study shows a high potential for optical metrology of graphene deposited on Ge/Si structures, due to its great sensitivity, repeatability, and flexibility, realized in a nondestructive way.
Label-free direct-optical biosensors such as surface-plasmon resonance (SPR) spectroscopy has become a gold standard in biochemical analytics in centralized laboratories. Biosensors based on photonic integrated circuits (PIC) are based on the same physical sensing mechanism: evanescent field sensing. PIC-based biosensors can play an important role in healthcare, especially for point-of-care diagnostics, if challenges for a transfer from research laboratory to industrial applications can be overcome. Research is at this threshold, which presents a great opportunity for innovative on-site analyses in the health and environmental sectors. A deeper understanding of the innovative PIC technology is possible by comparing it with the well-established SPR spectroscopy. In this work, we shortly introduce both technologies and reveal similarities and differences. Further, we review some latest advances and compare both technologies in terms of surface functionalization and sensor performance.
The successful integration of graphene into microelectronic devices depends strongly on the availability of fast and nondestructive characterization methods of graphene grown by CVD on large diameter production wafers [1-3] which are in the interest of the semiconductor industry. Here, a high-throughput optical metrology method for measuring the thickness and uniformity of large-area graphene sheets is demonstrated. The method is based on the combination of spectroscopic ellipsometry and normal incidence reflectometry in UV-Vis wavelength range (200-800 nm) with small light spots (~ 30 μm2) realized in wafer optical metrology tool. In the first step graphene layers were transferred on a SiO2/Si substrate in order to determine the optical constants of graphene by the combination of multi-angle ellipsometry and reflectometry. Then these data were used for the development of a process control recipe of CVD graphene on 200 mm Ge(100)/Si(100) wafers. The graphene layer quality was additionally monitored by Raman spectroscopy. Atomic force microscopy measurements were performed for micro topography evaluation. In consequence, a robust recipe for unambiguous thickness monitoring of all components of a multilayer film stack, including graphene, surface residuals or interface layer underneath graphene and surface roughness is developed. Optical monitoring of graphene thickness uniformity over a wafer has shown an excellent long term stability (s=0.004 nm) regardless of the growth of interfacial GeO2 and surface roughness. The sensitivity of the optical identification of graphene during microelectronic processing was evaluated.
This optical metrology technique with combined data collection exhibit a fast and highly precise method allowing one an unambiguous detection of graphene after transferring as well as after the CVD deposition process on a Ge(100)/Si(100) wafer. This approach is well suited for industrial applications due to its repeatability and flexibility.