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The application of Double Exposure Lithography (DEL) would enlarge the capability of 248 nm exposure technique to smaller pitch. We will use the DEL for the integration of critical layers for dedicated applications requiring resolution enhancement into 0.13 μm BiCMOS technology. In this paper we present the overlay precision and the focus difference of 1st and 2nd exposure as critical parameters of the DEL for k1 ≤ 0.3 lithography (100 nm half pitch) with binary masks (BIM). The realization of excellent overlay (OVL) accuracy is a main key of double exposure and double patterning techniques. We show the DEL requires primarily a good mask registration, when the wafer stays in the scanner for both exposures without alignment between 1st and 2nd exposure. The exposure tool overlay error is more a practical limit for double patterning lithography (DPL). Hence we prefer the DEL for the resolution enhancement, especially if we use the KrF high NA lithography tool for 130 nm generation. Experimental and simulated results show that the critical dimension uniformity (CDU) depends strongly on the overlay precision. The DEL results show CDU is not only affected by the OVL but also by an optical proximity effect of 1st and 2nd exposure and the mask registration. The CD uniformity of DEL demands a low focus difference between 1st and 2nd exposure and therefore requires a good focus repeatability of the exposure tool. The Depth of Focus (DOF) of 490 nm at stable CD of lines was achieved for DEL. If we change the focus of one of the exposures the CD-focus performance of spaces was reduced with simultaneous line position changing. CDU vs. focus difference between 1st and 2nd exposure demands a focus repeatability <100 nm for the exposure tool. Summary, the results show DEL has the potential to be a practical lithography enhancement method for device fabrication using high NA KrF tool generation.
Through Silicon Via (TSV) technology is a key feature of new 3D integration of circuits by creation of interconnections using vias, which go through the silicon wafer. Typically, the highly-selective Bosch Si etch process, characterized by a high etch rate and high aspect ratio and forming of scallops on the sidewalls is used. As presented in this paper, we have developed an experimental setup and a respective evaluation algorithm for the control and monitoring of very high aspect ratio TSV profiles by spectroscopic reflectometry. For this purpose square via arrays with lateral dimension from 3 to 10 μm were fabricated by a Bosch etch process and analyzed by our setup. By exploiting interference and diffraction effects of waves reflected from the top and bottom surfaces as well as from the side walls of the TSV patterns, the measurements provided etch depths, CD values and scallop periods. The results were compared with data obtained by a commercial wafer metrology tool. Aspect ratios of up to 35:1 were safely evaluable by our setup.
Through Silicon Via (TSV) technology is a key in 3D integration of circuits by the creation of interconnects using vias, which go through the full silicon wafer. Typically, a highly-selective Bosch Si etch process is used. It is characterized by a high etch rate at a high aspect ratio, whereby scallops on the sidewalls are generated. In this work, square via arrays with dimensions from 3 to 50 μm and up to 300 μm depth were fabricated and analyzed by spectroscopic reflectometry. The reflectometric data are compared to simulations by a novel theoretical approach. In order to simulate the reflectance spectra of TSV arrays, a combination of 2D and 3D rigorous coupled wave analysis was applied. Besides the via depth, the sidewall angle and the corner radius of the bottom profile were considered in the model. The general requirements on spectral resolution in TSV metrology are discussed.
The etching of high aspect ratio structures in silicon via the Bosch process is essential in modern technologies such as microelectromechanical systems (MEMS) and through‑silicon vias (TSV) fabrication. The process can be very demanding on the mask selectivity due to long etching times, and it has been shown that an Al2O3 hard mask is very suitable in this regard, as it offers significantly higher selectivity compared to the conventional SiO2 or resist masks. In this work, we employ a combination of Scanning Electron Microscopy (SEM), Spectroscopic Ellipsometry (SE) and X-Ray Photoelectron Spectroscopy (XPS) depth profiling to scrutinize the Al2O3 mask etching mechanism and therefore the origin of the extraordinary high selectivity. We demonstrate that by increasing the passivation step time, a thicker fluorocarbon polymer layer is formed on the Al2O3, and Al2O3 is then removed with a minuscule average etch rate of 0.01 nm/min. XPS depth profiling reveals that during Deep Reactive Ion Etching (DRIE) using the Bosch process, an AlFx layer is formed between the polymer and Al2O3. As AlFx is non-volatile, it requires sputtering to be removed. If the polymer layer is thick enough to attenuate the incoming ions such that their energy is not sufficient to lead to desorption of AlFx, such as when using a longer passivation time, the mask is not eroded. By investigating the surface after different amounts of DRIE cycles, we also obtained information about the formation rate of AlFx and the changes in the Al2O3 and polymer thicknesses over the course of a DRIE process. These findings further expand the knowledge of DRIE and can help process engineers to tailor the processes accordingly.
3D through silicon via profile metrology based on spectroscopic reflectometry for SOI applications
(2016)
Through-silicon via (TSV) technology is a key feature for 3D circuit integration. TSVs are formed by etching a vertical via and filling them with a conductive material for creation of interconnections which go through the silicon or silicon-on-insulator (SOI) wafer. The Bosch etch process on Deep Reactive Ion Etching (DRIE) is commonly used for this purpose. The etch profile defined by the critical dimensions (CDs) at the top and at the bottom, by the depth and by the scallop size on the sidewall needs to be monitored and well controlled.
In this work a nondestructive 3D metrology of deeply-etched structures with an aspect ratio of more than 10 and patterns with lateral dimensions from 2 to 7 μm in SOI wafer is proposed. Spectroscopic reflectometry in the spectral range of 250-800 nm using a production metrology tool was applied. The depth determinations based on different algorithms are compared.
The Pearson correlation coefficient between measured and calculated reflection is suggested as the most appropriate method. A simple method for top CD evaluation is proposed by the measurement of reflection and using the polynomial approximation of reflection versus TSV filling coefficient which is determined as ratio of CD to pitch. The 3D RCWA simulations confirm this dependence.
The two main features of the memristive devices which makes them the promising candidates for neuromorphic applications are low power consumption and CMOS compatibility. The monolithic integration of memristive devices with CMOS circuitry paves the way for in-memory computing. This chapter focuses on the factors governing the CMOS integration process. Firstly, the influence of CMOS baseline technology selection on the memristor module is briefly discussed. Secondly, the selection of metal level interconnects and their effect on the memristive device performance is explained. Further, the widely used deposition technique for the CMOS compatible memristive switching layers is presented. Finally, the implementation of the optimized process for the fabrication of the memristive module and its influence on the device performance is presented in terms of electrical characterization results.