TY - JOUR A1 - Anand, Ketan A1 - Schubert, Markus Andreas A1 - Corley-Wiciak, Agnieszka Anna A1 - Spirito, Davide A1 - Corley-Wiciak, Cedric A1 - Klesse, Wolfgang M. A1 - Mai, Andreas A1 - Tillack, Bernd A1 - Yamamoto, Yuji T1 - Lateral Selective SiGe Growth for Local Dislocation-Free SiGe-on-Insulator Virtual Substrate Fabrication JF - ECS Journal of Solid State Science and Technology N2 - Dislocation free local SiGe-on-insulator (SGOI) virtual substrate is fabricated using lateral selective SiGe growth by reduced pressure chemical vapor deposition. The lateral selective SiGe growth is performed around a ∼1.25 μm square Si (001) pillar in a cavity formed by HCl vapor phase etching of Si at 850 °C from side of SiO2/Si mesa structure on buried oxide. Smooth root mean square roughness of SiGe surface of 0.14 nm, which is determined by interface roughness between the sacrificially etched Si and the SiO2 cap, is obtained. Uniform Ge content of ∼40% in the laterally grown SiGe is observed. In the Si pillar, tensile strain of ∼0.65% is found which could be due to thermal expansion difference between SiO2 and Si. In the SiGe, tensile strain of ∼1.4% along 〈010〉 direction, which is higher compared to that along 〈110〉 direction, is observed. The tensile strain is induced from both [110] and [−110] directions. Threading dislocations in the SiGe are located only ∼400 nm from Si pillar and stacking faults are running towards 〈110〉 directions, resulting in the formation of a wide dislocation-free area in SiGe along 〈010〉 due to horizontal aspect ratio trapping. Y1 - 2023 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:526-opus4-17013 VL - 12 PB - Electrochemical Society (ECS); IOP ER - TY - CHAP A1 - Meister, Stefan A1 - Al-Saadi, Aws A1 - Franke, Bülent A. A1 - Mahdi, Shaimaa A1 - Kuhlow, Berndt A1 - Voigt, Karsten A1 - Tillack, Bernd A1 - Richter, Harald H. A1 - Zimmermann, Lars A1 - Ksianzou, Viachaslau A1 - Schrader, Sigurd A1 - Eichler, Hans J. T1 - Photonic crystal microcavities in SOI waveguides produced in a CMOS environment N2 - We have investigated microcavities in Silicon-on-Insolator (SOI) waveguides. The rectangular waveguides with 500 nm width are fabricated in the 220 nm silicon device layer. The microcavities are formed by one-dimensional photonic crystals in Fabry-Perot structure directly written in the waveguides. The SOI photonic structures are produced in a CMOS environment using 248 nm DUV lithography, where the waveguides as well as the photonic crystals are created in the same step using a single mask. In order to achieve a desired spectral shape of the filter function capable for several applications, a number of different cavities were investigated, e.g. single cavities of first and higher order as well as multi-cavity filters. The experimental results are compared with simulations of photonic crystal microcavities in strip waveguides. The spectral transmission function of such filters dependent on the design parameters are calculated by an analysis based on Finite-Difference-Time-Domain (FDTD) method. KW - silicon photonics KW - SOI waveguide KW - photonic crystal KW - band-pass filter KW - microcavity KW - FDTD simulation Y1 - 2010 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:526-opus4-15223 SP - 330 EP - 339 PB - Society of Photo-Optical Instrumentation Engineers (SPIE) ER -