TY - JOUR A1 - Fursenko, Oksana A1 - Lukosius, Mindaugas A1 - Bauer, Joachim A1 - Villringer, Claus A1 - Lux, Helge A1 - Bärwolf, Florian A1 - Lisker, Marco A1 - Mai, Andreas T1 - Diagnostic of graphene on Ge(100)/Si(100) in a 200 mm wafer Si technology environment by spectroscopic ellipsometry/reflectometry JF - Journal of Vacuum Science & Technology B N2 - Comprehensive diagnostics is a prerequisite for the application of graphene in semiconductor technologies. Here, the authors present long-term investigations of graphene on 200-mm Ge(100)/Si(100) wafers under clean room environmental conditions. Diagnostic of graphene was performed by a fast and nondestructive metrology method based on the combination of spectroscopic ellipsometry and reflectometry (SE/R), realized within a wafer optical metrology tool. A robust procedure for unambiguous thickness monitoring of a multilayer film stack, including graphene, interface layer GeOx underneath graphene, and surface roughness is developed and applied for process control. The authors found a relationship between the quality of graphene and the growth of GeOx beneath graphene. Enhanced oxidation of Ge beneath graphene was registered as a long-term process. SE/R measurements were validated and complemented using atomic force microscopy, scanning electron microscopy, Raman spectroscopy, and secondary ion mass spectrometry. This comparative study shows a high potential for optical metrology of graphene deposited on Ge/Si structures, due to its great sensitivity, repeatability, and flexibility, realized in a nondestructive way. Y1 - 2019 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:526-opus4-16083 VL - 37 IS - 6 PB - American Vacuum Society (AVS) ER - TY - JOUR A1 - Lukose, Rasuole A1 - Lisker, Marco A1 - Akhtar, Fatima A1 - Fraschke, Mirko A1 - Grabolla, T. A1 - Mai, Andreas A1 - Lukosius, Mindaugas T1 - Influence of plasma treatment on SiO2/Si and Si3N4/Si substrates for large-scale transfer of graphene JF - Scientific Reports N2 - One of the limiting factors of graphene integration into electronic, photonic, or sensing devices is the unavailability of large-scale graphene directly grown on the isolators. Therefore, it is necessary to transfer graphene from the donor growth wafers onto the isolating target wafers. In the present research, graphene was transferred from the chemical vapor deposited 200 mm Germanium/Silicon (Ge/Si) wafers onto isolating (SiO2/Si and Si3N4/Si) wafers by electrochemical delamination procedure, employing poly(methylmethacrylate) as an intermediate support layer. In order to influence the adhesion properties of graphene, the wettability properties of the target substrates were investigated in this study. To increase the adhesion of the graphene on the isolating surfaces, they were pre-treated with oxygen plasma prior the transfer process of graphene. The wetting contact angle measurements revealed the increase of the hydrophilicity after surface interaction with oxygen plasma, leading to improved adhesion of the graphene on 200 mm target wafers and possible proof-of-concept development of graphene-based devices in standard Si technologies. Y1 - 2021 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:526-opus4-14179 SN - 2045-2322 VL - 11 ER - TY - JOUR A1 - Elviretti, M. A1 - Lisker, Marco A1 - Lukose, Rasuole A1 - Lukosius, Mindaugas A1 - Akhtar, Fatima A1 - Mai, Andreas T1 - Reliable metal–graphene contact formation process flows in a CMOS-compatible environment JF - Nanoscale Advances N2 - The possibility of exploiting the enormous potential of graphene for microelectronics and photonics must go through the optimization of the graphene–metal contact. Achieving low contact resistance is essential for the consideration of graphene as a candidate material for electronic and photonic devices. This work has been carried out in an 8′′ wafer pilot-line for the integration of graphene into a CMOS environment. The main focus is to study the impact of the patterning of graphene and passivation on metal–graphene contact resistance. The latter is measured by means of transmission line measurement (TLM) with several contact designs. The presented approaches enable reproducible formation of contact resistivity as low as 660 Ω μm with a sheet resistance of 1.8 kΩ/□ by proper graphene patterning, passivation of the channel and a post-processing treatment such as annealing. Y1 - 2022 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:526-opus4-16581 VL - 4 SP - 4373 EP - 4380 PB - Royal Society of Chemistry (RSC) ER - TY - JOUR A1 - Dorai Swamy Reddy, Keerthi A1 - Pérez, Eduardo A1 - Baroni, Andrea A1 - Kalishettyhalli Mahadevaiah, Mamathamba A1 - Marschmeyer, Steffen A1 - Fraschke, Mirko A1 - Lisker, Marco A1 - Wenger, Christian A1 - Mai, Andreas T1 - Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance JF - The European Physical Journal B : Condensed Matter and Complex Systems N2 - Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal–insulator–metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO₂ dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm HfO₂ dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology. Y1 - 2024 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:526-opus4-19701 VL - 97 PB - Springer Nature ER - TY - JOUR A1 - Kalishettyhalli Mahadevaiah, Mamathamba A1 - Pérez, Eduardo A1 - Lisker, Marco A1 - Schubert, Markus Andreas A1 - Perez-Bosch Quesada, Emilio A1 - Wenger, Christian A1 - Mai, Andreas T1 - Modulating the Filamentary-Based Resistive Switching Properties of HfO₂ Memristive Devices by Adding Al₂O₃ Layers JF - Electronics N2 - The resistive switching properties of HfO₂ based 1T-1R memristive devices are electrically modified by adding ultra-thin layers of Al₂O₃ into the memristive device. Three different types of memristive stacks are fabricated in the 130 nm CMOS technology of IHP. The switching properties of the memristive devices are discussed with respect to forming voltages, low resistance state and high resistance state characteristics and their variabilities. The experimental I–V characteristics of set and reset operations are evaluated by using the quantum point contact model. The properties of the conduction filament in the on and off states of the memristive devices are discussed with respect to the model parameters obtained from the QPC fit. Y1 - 2022 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:526-opus4-16172 SN - 2079-9292 VL - 11 IS - 10 CY - MDPI ER - TY - CHAP A1 - Kalishettyhalli Mahadevaiah, Mamathamba A1 - Lisker, Marco A1 - Fraschke, Mirko A1 - Marschmeyer, Steffen A1 - Pérez, Eduardo A1 - Perez-Bosch Quesada, Emilio A1 - Wenger, Christian A1 - Mai, Andreas ED - Ziegler, Martin ED - Mussenbrock, Thomas ED - Kohlstedt, Hermann T1 - Integration of Memristive Devices into a 130 nm CMOS Baseline Technology T2 - Bio-Inspired Information Pathways: From Neuroscience to Neurotronics N2 - The two main features of the memristive devices which makes them the promising candidates for neuromorphic applications are low power consumption and CMOS compatibility. The monolithic integration of memristive devices with CMOS circuitry paves the way for in-memory computing. This chapter focuses on the factors governing the CMOS integration process. Firstly, the influence of CMOS baseline technology selection on the memristor module is briefly discussed. Secondly, the selection of metal level interconnects and their effect on the memristive device performance is explained. Further, the widely used deposition technique for the CMOS compatible memristive switching layers is presented. Finally, the implementation of the optimized process for the fabrication of the memristive module and its influence on the device performance is presented in terms of electrical characterization results. KW - CMOS compatibility KW - CMOS integration KW - memristive device KW - pristine current KW - resistive switching KW - thermal budget KW - encapsulation Y1 - 2024 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:526-opus4-18029 SN - 978-3-031-36705-2 SP - 177 EP - 190 PB - Springer International Publishing CY - Cham ER -