TY - JOUR A1 - Dorai Swamy Reddy, Keerthi A1 - Pérez, Eduardo A1 - Baroni, Andrea A1 - Kalishettyhalli Mahadevaiah, Mamathamba A1 - Marschmeyer, Steffen A1 - Fraschke, Mirko A1 - Lisker, Marco A1 - Wenger, Christian A1 - Mai, Andreas T1 - Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance JF - The European Physical Journal B : Condensed Matter and Complex Systems N2 - Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal–insulator–metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO₂ dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm HfO₂ dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology. Y1 - 2024 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:526-opus4-19701 VL - 97 PB - Springer Nature ER - TY - CHAP A1 - Kalishettyhalli Mahadevaiah, Mamathamba A1 - Lisker, Marco A1 - Fraschke, Mirko A1 - Marschmeyer, Steffen A1 - Pérez, Eduardo A1 - Perez-Bosch Quesada, Emilio A1 - Wenger, Christian A1 - Mai, Andreas ED - Ziegler, Martin ED - Mussenbrock, Thomas ED - Kohlstedt, Hermann T1 - Integration of Memristive Devices into a 130 nm CMOS Baseline Technology T2 - Bio-Inspired Information Pathways: From Neuroscience to Neurotronics N2 - The two main features of the memristive devices which makes them the promising candidates for neuromorphic applications are low power consumption and CMOS compatibility. The monolithic integration of memristive devices with CMOS circuitry paves the way for in-memory computing. This chapter focuses on the factors governing the CMOS integration process. Firstly, the influence of CMOS baseline technology selection on the memristor module is briefly discussed. Secondly, the selection of metal level interconnects and their effect on the memristive device performance is explained. Further, the widely used deposition technique for the CMOS compatible memristive switching layers is presented. Finally, the implementation of the optimized process for the fabrication of the memristive module and its influence on the device performance is presented in terms of electrical characterization results. KW - CMOS compatibility KW - CMOS integration KW - memristive device KW - pristine current KW - resistive switching KW - thermal budget KW - encapsulation Y1 - 2024 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:526-opus4-18029 SN - 978-3-031-36705-2 SP - 177 EP - 190 PB - Springer International Publishing CY - Cham ER -