TY - JOUR A1 - Drost, Martin A1 - Marschmeyer, Steffen A1 - Fraschke, Mirko A1 - Fursenko, Oksana A1 - Bärwolf, Florian A1 - Costina, Ioan A1 - Kalishettyhalli Mahadevaiah, Mamathamba A1 - Lisker, Marco T1 - Etch mechanism of an Al₂O₃ hard mask in the Bosch process JF - Micro and Nano Engineering N2 - The etching of high aspect ratio structures in silicon via the Bosch process is essential in modern technologies such as microelectromechanical systems (MEMS) and through‑silicon vias (TSV) fabrication. The process can be very demanding on the mask selectivity due to long etching times, and it has been shown that an Al2O3 hard mask is very suitable in this regard, as it offers significantly higher selectivity compared to the conventional SiO2 or resist masks. In this work, we employ a combination of Scanning Electron Microscopy (SEM), Spectroscopic Ellipsometry (SE) and X-Ray Photoelectron Spectroscopy (XPS) depth profiling to scrutinize the Al2O3 mask etching mechanism and therefore the origin of the extraordinary high selectivity. We demonstrate that by increasing the passivation step time, a thicker fluorocarbon polymer layer is formed on the Al2O3, and Al2O3 is then removed with a minuscule average etch rate of 0.01 nm/min. XPS depth profiling reveals that during Deep Reactive Ion Etching (DRIE) using the Bosch process, an AlFx layer is formed between the polymer and Al2O3. As AlFx is non-volatile, it requires sputtering to be removed. If the polymer layer is thick enough to attenuate the incoming ions such that their energy is not sufficient to lead to desorption of AlFx, such as when using a longer passivation time, the mask is not eroded. By investigating the surface after different amounts of DRIE cycles, we also obtained information about the formation rate of AlFx and the changes in the Al2O3 and polymer thicknesses over the course of a DRIE process. These findings further expand the knowledge of DRIE and can help process engineers to tailor the processes accordingly. KW - Bosch process KW - deep reactive ion etching KW - aluminum oxide Y1 - 2022 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:526-opus4-15678 SN - 2590-0072 VL - 14 PB - Elsevier ER - TY - JOUR A1 - Lukose, Rasuole A1 - Lisker, Marco A1 - Akhtar, Fatima A1 - Fraschke, Mirko A1 - Grabolla, T. A1 - Mai, Andreas A1 - Lukosius, Mindaugas T1 - Influence of plasma treatment on SiO2/Si and Si3N4/Si substrates for large-scale transfer of graphene JF - Scientific Reports N2 - One of the limiting factors of graphene integration into electronic, photonic, or sensing devices is the unavailability of large-scale graphene directly grown on the isolators. Therefore, it is necessary to transfer graphene from the donor growth wafers onto the isolating target wafers. In the present research, graphene was transferred from the chemical vapor deposited 200 mm Germanium/Silicon (Ge/Si) wafers onto isolating (SiO2/Si and Si3N4/Si) wafers by electrochemical delamination procedure, employing poly(methylmethacrylate) as an intermediate support layer. In order to influence the adhesion properties of graphene, the wettability properties of the target substrates were investigated in this study. To increase the adhesion of the graphene on the isolating surfaces, they were pre-treated with oxygen plasma prior the transfer process of graphene. The wetting contact angle measurements revealed the increase of the hydrophilicity after surface interaction with oxygen plasma, leading to improved adhesion of the graphene on 200 mm target wafers and possible proof-of-concept development of graphene-based devices in standard Si technologies. Y1 - 2021 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:526-opus4-14179 SN - 2045-2322 VL - 11 ER - TY - JOUR A1 - Dorai Swamy Reddy, Keerthi A1 - Pérez, Eduardo A1 - Baroni, Andrea A1 - Kalishettyhalli Mahadevaiah, Mamathamba A1 - Marschmeyer, Steffen A1 - Fraschke, Mirko A1 - Lisker, Marco A1 - Wenger, Christian A1 - Mai, Andreas T1 - Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance JF - The European Physical Journal B : Condensed Matter and Complex Systems N2 - Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal–insulator–metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO₂ dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm HfO₂ dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology. Y1 - 2024 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:526-opus4-19701 VL - 97 PB - Springer Nature ER - TY - CHAP A1 - Kalishettyhalli Mahadevaiah, Mamathamba A1 - Lisker, Marco A1 - Fraschke, Mirko A1 - Marschmeyer, Steffen A1 - Pérez, Eduardo A1 - Perez-Bosch Quesada, Emilio A1 - Wenger, Christian A1 - Mai, Andreas ED - Ziegler, Martin ED - Mussenbrock, Thomas ED - Kohlstedt, Hermann T1 - Integration of Memristive Devices into a 130 nm CMOS Baseline Technology T2 - Bio-Inspired Information Pathways: From Neuroscience to Neurotronics N2 - The two main features of the memristive devices which makes them the promising candidates for neuromorphic applications are low power consumption and CMOS compatibility. The monolithic integration of memristive devices with CMOS circuitry paves the way for in-memory computing. This chapter focuses on the factors governing the CMOS integration process. Firstly, the influence of CMOS baseline technology selection on the memristor module is briefly discussed. Secondly, the selection of metal level interconnects and their effect on the memristive device performance is explained. Further, the widely used deposition technique for the CMOS compatible memristive switching layers is presented. Finally, the implementation of the optimized process for the fabrication of the memristive module and its influence on the device performance is presented in terms of electrical characterization results. KW - CMOS compatibility KW - CMOS integration KW - memristive device KW - pristine current KW - resistive switching KW - thermal budget KW - encapsulation Y1 - 2024 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:526-opus4-18029 SN - 978-3-031-36705-2 SP - 177 EP - 190 PB - Springer International Publishing CY - Cham ER -