TY - JOUR A1 - Lisker, Marco A1 - Kalishettyhalli Mahadevaiah, Mamathamba A1 - Dorai Swamy Reddy, Keerthi T1 - Plasma-enhanced atomic layer deposition of silicon nitride for front-end-of-line applications JF - Journal of Vacuum Science & Technology A N2 - SiN deposition at low temperatures using the plasma-enhanced atomic layer deposition (PEALD) process is gaining momentum. A high-quality SiN layer deposited using a lower thermal budget and low wet etch rates are desired for front-end-of-line applications in semiconductor industries. In this study, deposition of PEALD SiN is investigated by utilizing a highly reactive trisilylamine silicon precursor and three different reaction partners for a nitrogen precursor. The quality of PEALD SiN layers is compared with the reference standard, low-pressure chemical vapor deposition SiN layers. The properties of different SiN layers are interpreted using FTIR and XPS material characterization techniques. Furthermore, the wet etch rates of as-deposited and annealed PEALD SiN layers are investigated. Finally, the conformality of PEALD SiN layers is assessed in trench and horizontal high aspect ratio structures. Y1 - 2023 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:526-opus4-17699 SN - 0734-2101 VL - 41 IS - 4 PB - American Vacuum Society (AVS) ER - TY - JOUR A1 - Dorai Swamy Reddy, Keerthi A1 - Pérez, Eduardo A1 - Baroni, Andrea A1 - Kalishettyhalli Mahadevaiah, Mamathamba A1 - Marschmeyer, Steffen A1 - Fraschke, Mirko A1 - Lisker, Marco A1 - Wenger, Christian A1 - Mai, Andreas T1 - Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance JF - The European Physical Journal B : Condensed Matter and Complex Systems N2 - Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal–insulator–metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO₂ dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm HfO₂ dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology. Y1 - 2024 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:526-opus4-19701 VL - 97 PB - Springer Nature ER -