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    <id>1970</id>
    <completedYear>2024</completedYear>
    <publishedYear/>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume>97</volume>
    <type>article</type>
    <publisherName>Springer Nature</publisherName>
    <publisherPlace/>
    <creatingCorporation/>
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    <belongsToBibliography>1</belongsToBibliography>
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    <title language="eng">Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance</title>
    <abstract language="eng">Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal–insulator–metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO₂ dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm HfO₂ dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology.</abstract>
    <parentTitle language="eng">The European Physical Journal B : Condensed Matter and Complex Systems</parentTitle>
    <identifier type="urn">urn:nbn:de:kobv:526-opus4-19701</identifier>
    <enrichment key="opus.import.date">2024-12-03T07:25:21+00:00</enrichment>
    <enrichment key="opus.source">sword</enrichment>
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    <enrichment key="DOI_VoR">https://doi.org/10.1140/epjb/s10051-024-00821-1</enrichment>
    <enrichment key="SourceTitle">Dorai Swamy Reddy, K., Pérez, E., Baroni, A. et al. Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance. Eur. Phys. J. B 97, 181 (2024). https://doi.org/10.1140/epjb/s10051-024-00821-1</enrichment>
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    <licence>Creative Commons - CC BY - Namensnennung 4.0 International</licence>
    <author>Keerthi Dorai Swamy Reddy</author>
    <author>Eduardo Pérez</author>
    <author>Andrea Baroni</author>
    <author>Mamathamba Kalishettyhalli Mahadevaiah</author>
    <author>Steffen Marschmeyer</author>
    <author>Mirko Fraschke</author>
    <author>Marco Lisker</author>
    <author>Christian Wenger</author>
    <author>Andreas Mai</author>
    <collection role="ddc" number="006">Spezielle Computerverfahren</collection>
    <collection role="ddc" number="621">Angewandte Physik</collection>
    <collection role="institutes" number="">Fachbereich Ingenieur- und Naturwissenschaften</collection>
    <collection role="open_access" number="">open_access</collection>
    <collection role="Import" number="import">Import</collection>
    <collection role="green_open_access" number="4">Hybrid Open Access</collection>
    <thesisPublisher>Technische Hochschule Wildau</thesisPublisher>
    <file>https://opus4.kobv.de/opus4-th-wildau/files/1970/s10051-024-00821-1.pdf</file>
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