@article{DrostMarschmeyerFraschkeetal.2022, author = {Drost, Martin and Marschmeyer, Steffen and Fraschke, Mirko and Fursenko, Oksana and B{\"a}rwolf, Florian and Costina, Ioan and Kalishettyhalli Mahadevaiah, Mamathamba and Lisker, Marco}, title = {Etch mechanism of an Al₂O₃ hard mask in the Bosch process}, series = {Micro and Nano Engineering}, volume = {14}, journal = {Micro and Nano Engineering}, publisher = {Elsevier}, issn = {2590-0072}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:526-opus4-15678}, year = {2022}, abstract = {The etching of high aspect ratio structures in silicon via the Bosch process is essential in modern technologies such as microelectromechanical systems (MEMS) and through‑silicon vias (TSV) fabrication. The process can be very demanding on the mask selectivity due to long etching times, and it has been shown that an Al2O3 hard mask is very suitable in this regard, as it offers significantly higher selectivity compared to the conventional SiO2 or resist masks. In this work, we employ a combination of Scanning Electron Microscopy (SEM), Spectroscopic Ellipsometry (SE) and X-Ray Photoelectron Spectroscopy (XPS) depth profiling to scrutinize the Al2O3 mask etching mechanism and therefore the origin of the extraordinary high selectivity. We demonstrate that by increasing the passivation step time, a thicker fluorocarbon polymer layer is formed on the Al2O3, and Al2O3 is then removed with a minuscule average etch rate of 0.01 nm/min. XPS depth profiling reveals that during Deep Reactive Ion Etching (DRIE) using the Bosch process, an AlFx layer is formed between the polymer and Al2O3. As AlFx is non-volatile, it requires sputtering to be removed. If the polymer layer is thick enough to attenuate the incoming ions such that their energy is not sufficient to lead to desorption of AlFx, such as when using a longer passivation time, the mask is not eroded. By investigating the surface after different amounts of DRIE cycles, we also obtained information about the formation rate of AlFx and the changes in the Al2O3 and polymer thicknesses over the course of a DRIE process. These findings further expand the knowledge of DRIE and can help process engineers to tailor the processes accordingly.}, language = {en} } @inproceedings{FursenkoBauerMarschmeyer2016, author = {Fursenko, Oksana and Bauer, Joachim and Marschmeyer, Steffen}, title = {3D through silicon via profile metrology based on spectroscopic reflectometry for SOI applications}, publisher = {Society of Photo-Optical Instrumentation Engineers (SPIE)}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:526-opus4-15272}, pages = {268 -- 273}, year = {2016}, abstract = {Through-silicon via (TSV) technology is a key feature for 3D circuit integration. TSVs are formed by etching a vertical via and filling them with a conductive material for creation of interconnections which go through the silicon or silicon-on-insulator (SOI) wafer. The Bosch etch process on Deep Reactive Ion Etching (DRIE) is commonly used for this purpose. The etch profile defined by the critical dimensions (CDs) at the top and at the bottom, by the depth and by the scallop size on the sidewall needs to be monitored and well controlled. In this work a nondestructive 3D metrology of deeply-etched structures with an aspect ratio of more than 10 and patterns with lateral dimensions from 2 to 7 μm in SOI wafer is proposed. Spectroscopic reflectometry in the spectral range of 250-800 nm using a production metrology tool was applied. The depth determinations based on different algorithms are compared. The Pearson correlation coefficient between measured and calculated reflection is suggested as the most appropriate method. A simple method for top CD evaluation is proposed by the measurement of reflection and using the polynomial approximation of reflection versus TSV filling coefficient which is determined as ratio of CD to pitch. The 3D RCWA simulations confirm this dependence.}, language = {en} } @inproceedings{BauerHeinrichFursenkoetal.2017, author = {Bauer, Joachim and Heinrich, Friedhelm and Fursenko, Oksana and Marschmeyer, Steffen and Bluemich, Adrian and Pulwer, Silvio and Steglich, Patrick and Villringer, Claus and Mai, Andreas and Schrader, Sigurd}, title = {Very high aspect ratio through silicon via reflectometry}, series = {Proceedings of SPIE}, booktitle = {Proceedings of SPIE}, issn = {1996-756X}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:526-opus4-13758}, year = {2017}, abstract = {Through Silicon Via (TSV) technology is a key feature of new 3D integration of circuits by creation of interconnections using vias, which go through the silicon wafer. Typically, the highly-selective Bosch Si etch process, characterized by a high etch rate and high aspect ratio and forming of scallops on the sidewalls is used. As presented in this paper, we have developed an experimental setup and a respective evaluation algorithm for the control and monitoring of very high aspect ratio TSV profiles by spectroscopic reflectometry. For this purpose square via arrays with lateral dimension from 3 to 10 μm were fabricated by a Bosch etch process and analyzed by our setup. By exploiting interference and diffraction effects of waves reflected from the top and bottom surfaces as well as from the side walls of the TSV patterns, the measurements provided etch depths, CD values and scallop periods. The results were compared with data obtained by a commercial wafer metrology tool. Aspect ratios of up to 35:1 were safely evaluable by our setup.}, language = {en} } @article{DoraiSwamyReddyPerezBaronietal.2024, author = {Dorai Swamy Reddy, Keerthi and P{\´e}rez, Eduardo and Baroni, Andrea and Kalishettyhalli Mahadevaiah, Mamathamba and Marschmeyer, Steffen and Fraschke, Mirko and Lisker, Marco and Wenger, Christian and Mai, Andreas}, title = {Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance}, series = {The European Physical Journal B : Condensed Matter and Complex Systems}, volume = {97}, journal = {The European Physical Journal B : Condensed Matter and Complex Systems}, publisher = {Springer Nature}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:526-opus4-19701}, year = {2024}, abstract = {Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal-insulator-metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO₂ dielectric thickness from 8 nm to 5 nm. Additionally, 5\% Al-doped 4 nm HfO₂ dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology.}, language = {en} } @incollection{KalishettyhalliMahadevaiahLiskerFraschkeetal.2024, author = {Kalishettyhalli Mahadevaiah, Mamathamba and Lisker, Marco and Fraschke, Mirko and Marschmeyer, Steffen and P{\´e}rez, Eduardo and Perez-Bosch Quesada, Emilio and Wenger, Christian and Mai, Andreas}, title = {Integration of Memristive Devices into a 130 nm CMOS Baseline Technology}, series = {Bio-Inspired Information Pathways: From Neuroscience to Neurotronics}, booktitle = {Bio-Inspired Information Pathways: From Neuroscience to Neurotronics}, editor = {Ziegler, Martin and Mussenbrock, Thomas and Kohlstedt, Hermann}, publisher = {Springer International Publishing}, address = {Cham}, isbn = {978-3-031-36705-2}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:526-opus4-18029}, publisher = {Technische Hochschule Wildau}, pages = {177 -- 190}, year = {2024}, abstract = {The two main features of the memristive devices which makes them the promising candidates for neuromorphic applications are low power consumption and CMOS compatibility. The monolithic integration of memristive devices with CMOS circuitry paves the way for in-memory computing. This chapter focuses on the factors governing the CMOS integration process. Firstly, the influence of CMOS baseline technology selection on the memristor module is briefly discussed. Secondly, the selection of metal level interconnects and their effect on the memristive device performance is explained. Further, the widely used deposition technique for the CMOS compatible memristive switching layers is presented. Finally, the implementation of the optimized process for the fabrication of the memristive module and its influence on the device performance is presented in terms of electrical characterization results.}, language = {en} } @article{BauerHeinrichVillasmuntaetal.2025, author = {Bauer, Joachim and Heinrich, Friedhelm and Villasmunta, Francesco and Villringer, Claus and Reck, Johanna and Peters, Sven and Treffer, Alexander and Kuhnt, Christian and Marschmeyer, Steffen and Fursenko, Oksana and Stolarek, David and Mai, Andreas and Regehly, Martin}, title = {Reflectometric method for measuring residual oxides in through-silicon vias for 3D chip integration}, series = {Optics Express}, volume = {33}, journal = {Optics Express}, number = {15}, publisher = {Optica}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:526-opus4-20633}, pages = {32175 -- 32189}, year = {2025}, abstract = {A significant aspect of fabricating 3D chip architectures is ensuring proper contact between the different layers of the chip, which often requires removing the underside of isolation layers before filling vias with conductive material. Currently, scanning electron microscopy is the established method for investigating such structures. In this paper, we propose a rapid, non-destructive optical analysis technique for the simultaneous measurement of through-silicon vias (TSV) depths, silicon wafer thickness, and residual oxide thickness. The proposed method utilizes Fourier peak shift analysis (FPSA) of reflectance measurements in the near-infrared (1200 nm—2200 nm) spectral regions. The application of FPSA to representative samples taken from a commercial TSV integration process for MEMS and CMOS fabrication demonstrated good agreement with reference scanning electron microscopy measurements, confirming the feasibility of the method for in-line and in-situ metrology. The results indicate that FPSA has great potential for real-time process monitoring and control during 3D chip manufacturing.}, language = {en} } @article{BauerFursenkoMarschmeyeretal.2019, author = {Bauer, Joachim and Fursenko, Oksana and Marschmeyer, Steffen and Heinrich, Friedhelm and Villasmunta, Francesco and Villringer, Claus and Zesch, Christoph and Schrader, Sigurd}, title = {Spectroscopic reflectometry for characterization of Through Silicon Via profile of Bosch etching process}, series = {Journal of Vacuum Science \& Technology B}, volume = {37}, journal = {Journal of Vacuum Science \& Technology B}, number = {6}, publisher = {American Vacuum Society (AVS)}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:526-opus4-16093}, year = {2019}, abstract = {Through Silicon Via (TSV) technology is a key in 3D integration of circuits by the creation of interconnects using vias, which go through the full silicon wafer. Typically, a highly-selective Bosch Si etch process is used. It is characterized by a high etch rate at a high aspect ratio, whereby scallops on the sidewalls are generated. In this work, square via arrays with dimensions from 3 to 50 μm and up to 300 μm depth were fabricated and analyzed by spectroscopic reflectometry. The reflectometric data are compared to simulations by a novel theoretical approach. In order to simulate the reflectance spectra of TSV arrays, a combination of 2D and 3D rigorous coupled wave analysis was applied. Besides the via depth, the sidewall angle and the corner radius of the bottom profile were considered in the model. The general requirements on spectral resolution in TSV metrology are discussed.}, language = {en} }