@article{DrostMarschmeyerFraschkeetal.2022, author = {Drost, Martin and Marschmeyer, Steffen and Fraschke, Mirko and Fursenko, Oksana and B{\"a}rwolf, Florian and Costina, Ioan and Kalishettyhalli Mahadevaiah, Mamathamba and Lisker, Marco}, title = {Etch mechanism of an Al₂O₃ hard mask in the Bosch process}, series = {Micro and Nano Engineering}, volume = {14}, journal = {Micro and Nano Engineering}, publisher = {Elsevier}, issn = {2590-0072}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:526-opus4-15678}, year = {2022}, abstract = {The etching of high aspect ratio structures in silicon via the Bosch process is essential in modern technologies such as microelectromechanical systems (MEMS) and through‑silicon vias (TSV) fabrication. The process can be very demanding on the mask selectivity due to long etching times, and it has been shown that an Al2O3 hard mask is very suitable in this regard, as it offers significantly higher selectivity compared to the conventional SiO2 or resist masks. In this work, we employ a combination of Scanning Electron Microscopy (SEM), Spectroscopic Ellipsometry (SE) and X-Ray Photoelectron Spectroscopy (XPS) depth profiling to scrutinize the Al2O3 mask etching mechanism and therefore the origin of the extraordinary high selectivity. We demonstrate that by increasing the passivation step time, a thicker fluorocarbon polymer layer is formed on the Al2O3, and Al2O3 is then removed with a minuscule average etch rate of 0.01 nm/min. XPS depth profiling reveals that during Deep Reactive Ion Etching (DRIE) using the Bosch process, an AlFx layer is formed between the polymer and Al2O3. As AlFx is non-volatile, it requires sputtering to be removed. If the polymer layer is thick enough to attenuate the incoming ions such that their energy is not sufficient to lead to desorption of AlFx, such as when using a longer passivation time, the mask is not eroded. By investigating the surface after different amounts of DRIE cycles, we also obtained information about the formation rate of AlFx and the changes in the Al2O3 and polymer thicknesses over the course of a DRIE process. These findings further expand the knowledge of DRIE and can help process engineers to tailor the processes accordingly.}, language = {en} } @article{LiskerKalishettyhalliMahadevaiahDoraiSwamyReddy2023, author = {Lisker, Marco and Kalishettyhalli Mahadevaiah, Mamathamba and Dorai Swamy Reddy, Keerthi}, title = {Plasma-enhanced atomic layer deposition of silicon nitride for front-end-of-line applications}, series = {Journal of Vacuum Science \& Technology A}, volume = {41}, journal = {Journal of Vacuum Science \& Technology A}, number = {4}, publisher = {American Vacuum Society (AVS)}, issn = {0734-2101}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:526-opus4-17699}, year = {2023}, abstract = {SiN deposition at low temperatures using the plasma-enhanced atomic layer deposition (PEALD) process is gaining momentum. A high-quality SiN layer deposited using a lower thermal budget and low wet etch rates are desired for front-end-of-line applications in semiconductor industries. In this study, deposition of PEALD SiN is investigated by utilizing a highly reactive trisilylamine silicon precursor and three different reaction partners for a nitrogen precursor. The quality of PEALD SiN layers is compared with the reference standard, low-pressure chemical vapor deposition SiN layers. The properties of different SiN layers are interpreted using FTIR and XPS material characterization techniques. Furthermore, the wet etch rates of as-deposited and annealed PEALD SiN layers are investigated. Finally, the conformality of PEALD SiN layers is assessed in trench and horizontal high aspect ratio structures.}, language = {en} } @article{FursenkoLukosiusBaueretal.2019, author = {Fursenko, Oksana and Lukosius, Mindaugas and Bauer, Joachim and Villringer, Claus and Lux, Helge and B{\"a}rwolf, Florian and Lisker, Marco and Mai, Andreas}, title = {Diagnostic of graphene on Ge(100)/Si(100) in a 200 mm wafer Si technology environment by spectroscopic ellipsometry/reflectometry}, series = {Journal of Vacuum Science \& Technology B}, volume = {37}, journal = {Journal of Vacuum Science \& Technology B}, number = {6}, publisher = {American Vacuum Society (AVS)}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:526-opus4-16083}, year = {2019}, abstract = {Comprehensive diagnostics is a prerequisite for the application of graphene in semiconductor technologies. Here, the authors present long-term investigations of graphene on 200-mm Ge(100)/Si(100) wafers under clean room environmental conditions. Diagnostic of graphene was performed by a fast and nondestructive metrology method based on the combination of spectroscopic ellipsometry and reflectometry (SE/R), realized within a wafer optical metrology tool. A robust procedure for unambiguous thickness monitoring of a multilayer film stack, including graphene, interface layer GeOx underneath graphene, and surface roughness is developed and applied for process control. The authors found a relationship between the quality of graphene and the growth of GeOx beneath graphene. Enhanced oxidation of Ge beneath graphene was registered as a long-term process. SE/R measurements were validated and complemented using atomic force microscopy, scanning electron microscopy, Raman spectroscopy, and secondary ion mass spectrometry. This comparative study shows a high potential for optical metrology of graphene deposited on Ge/Si structures, due to its great sensitivity, repeatability, and flexibility, realized in a nondestructive way.}, language = {en} } @article{LukoseLiskerAkhtaretal.2021, author = {Lukose, Rasuole and Lisker, Marco and Akhtar, Fatima and Fraschke, Mirko and Grabolla, T. and Mai, Andreas and Lukosius, Mindaugas}, title = {Influence of plasma treatment on SiO2/Si and Si3N4/Si substrates for large-scale transfer of graphene}, series = {Scientific Reports}, volume = {11}, journal = {Scientific Reports}, issn = {2045-2322}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:526-opus4-14179}, year = {2021}, abstract = {One of the limiting factors of graphene integration into electronic, photonic, or sensing devices is the unavailability of large-scale graphene directly grown on the isolators. Therefore, it is necessary to transfer graphene from the donor growth wafers onto the isolating target wafers. In the present research, graphene was transferred from the chemical vapor deposited 200 mm Germanium/Silicon (Ge/Si) wafers onto isolating (SiO2/Si and Si3N4/Si) wafers by electrochemical delamination procedure, employing poly(methylmethacrylate) as an intermediate support layer. In order to influence the adhesion properties of graphene, the wettability properties of the target substrates were investigated in this study. To increase the adhesion of the graphene on the isolating surfaces, they were pre-treated with oxygen plasma prior the transfer process of graphene. The wetting contact angle measurements revealed the increase of the hydrophilicity after surface interaction with oxygen plasma, leading to improved adhesion of the graphene on 200 mm target wafers and possible proof-of-concept development of graphene-based devices in standard Si technologies.}, language = {en} } @article{ElvirettiLiskerLukoseetal.2022, author = {Elviretti, M. and Lisker, Marco and Lukose, Rasuole and Lukosius, Mindaugas and Akhtar, Fatima and Mai, Andreas}, title = {Reliable metal-graphene contact formation process flows in a CMOS-compatible environment}, series = {Nanoscale Advances}, volume = {4}, journal = {Nanoscale Advances}, publisher = {Royal Society of Chemistry (RSC)}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:526-opus4-16581}, pages = {4373 -- 4380}, year = {2022}, abstract = {The possibility of exploiting the enormous potential of graphene for microelectronics and photonics must go through the optimization of the graphene-metal contact. Achieving low contact resistance is essential for the consideration of graphene as a candidate material for electronic and photonic devices. This work has been carried out in an 8′′ wafer pilot-line for the integration of graphene into a CMOS environment. The main focus is to study the impact of the patterning of graphene and passivation on metal-graphene contact resistance. The latter is measured by means of transmission line measurement (TLM) with several contact designs. The presented approaches enable reproducible formation of contact resistivity as low as 660 Ω μm with a sheet resistance of 1.8 kΩ/□ by proper graphene patterning, passivation of the channel and a post-processing treatment such as annealing.}, language = {en} } @article{DoraiSwamyReddyPerezBaronietal.2024, author = {Dorai Swamy Reddy, Keerthi and P{\´e}rez, Eduardo and Baroni, Andrea and Kalishettyhalli Mahadevaiah, Mamathamba and Marschmeyer, Steffen and Fraschke, Mirko and Lisker, Marco and Wenger, Christian and Mai, Andreas}, title = {Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance}, series = {The European Physical Journal B : Condensed Matter and Complex Systems}, volume = {97}, journal = {The European Physical Journal B : Condensed Matter and Complex Systems}, publisher = {Springer Nature}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:526-opus4-19701}, year = {2024}, abstract = {Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal-insulator-metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO₂ dielectric thickness from 8 nm to 5 nm. Additionally, 5\% Al-doped 4 nm HfO₂ dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology.}, language = {en} } @article{KalishettyhalliMahadevaiahPerezLiskeretal.2022, author = {Kalishettyhalli Mahadevaiah, Mamathamba and P{\´e}rez, Eduardo and Lisker, Marco and Schubert, Markus Andreas and Perez-Bosch Quesada, Emilio and Wenger, Christian and Mai, Andreas}, title = {Modulating the Filamentary-Based Resistive Switching Properties of HfO₂ Memristive Devices by Adding Al₂O₃ Layers}, series = {Electronics}, volume = {11}, journal = {Electronics}, number = {10}, address = {MDPI}, issn = {2079-9292}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:526-opus4-16172}, year = {2022}, abstract = {The resistive switching properties of HfO₂ based 1T-1R memristive devices are electrically modified by adding ultra-thin layers of Al₂O₃ into the memristive device. Three different types of memristive stacks are fabricated in the 130 nm CMOS technology of IHP. The switching properties of the memristive devices are discussed with respect to forming voltages, low resistance state and high resistance state characteristics and their variabilities. The experimental I-V characteristics of set and reset operations are evaluated by using the quantum point contact model. The properties of the conduction filament in the on and off states of the memristive devices are discussed with respect to the model parameters obtained from the QPC fit.}, language = {en} } @incollection{KalishettyhalliMahadevaiahLiskerFraschkeetal.2024, author = {Kalishettyhalli Mahadevaiah, Mamathamba and Lisker, Marco and Fraschke, Mirko and Marschmeyer, Steffen and P{\´e}rez, Eduardo and Perez-Bosch Quesada, Emilio and Wenger, Christian and Mai, Andreas}, title = {Integration of Memristive Devices into a 130 nm CMOS Baseline Technology}, series = {Bio-Inspired Information Pathways: From Neuroscience to Neurotronics}, booktitle = {Bio-Inspired Information Pathways: From Neuroscience to Neurotronics}, editor = {Ziegler, Martin and Mussenbrock, Thomas and Kohlstedt, Hermann}, publisher = {Springer International Publishing}, address = {Cham}, isbn = {978-3-031-36705-2}, url = {http://nbn-resolving.de/urn:nbn:de:kobv:526-opus4-18029}, publisher = {Technische Hochschule Wildau}, pages = {177 -- 190}, year = {2024}, abstract = {The two main features of the memristive devices which makes them the promising candidates for neuromorphic applications are low power consumption and CMOS compatibility. The monolithic integration of memristive devices with CMOS circuitry paves the way for in-memory computing. This chapter focuses on the factors governing the CMOS integration process. Firstly, the influence of CMOS baseline technology selection on the memristor module is briefly discussed. Secondly, the selection of metal level interconnects and their effect on the memristive device performance is explained. Further, the widely used deposition technique for the CMOS compatible memristive switching layers is presented. Finally, the implementation of the optimized process for the fabrication of the memristive module and its influence on the device performance is presented in terms of electrical characterization results.}, language = {en} }